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Adventurer
Adventurer
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Registered: ‎02-08-2013

7-series ISERDES OVERSAMPLE bit order output

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Hi,

 

I'm using Planahead 14.6 - Can someone from Xilinx please confirm what the actual bit order output is from the ISERDES primitive in a Kintex-7 in OVERSAMPLE mode?

 

The reason I ask is that as most topics of this nature online confirm, the documentation is contradictory and erroneous and I'm getting odd patterns with my oversampling deskew algorithm and don't have a scope fast enough to see for myself. I'm running chipscope but If I can't be sure what order the data is coming out it's useless.

 

Are the relevant outputs Q1 to Q4 and is Q1 the first sample?

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Adventurer
Adventurer
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Registered: ‎02-08-2013

Re: 7-series ISERDES OVERSAMPLE bit order output

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OK folks, it turns out the diagrams in the manual is correct:

 

CLK = CLK0

CLKB = CLK180 (or CLK0n)

OCLK = CLK90

OCLKB = CLK270 (or CLK90n)

 

Then:

 

Q1 = Sample 1

Q2 = Sample 3

Q3 = Sample 2

Q4 = Sample 4

 

This is how the testbench is behaving, and how it is implemented in the whitepaper Xapp523. Here is the diagram from the SelectIO datasheet:

 

ug471_OVERSAMPLE_diagram.jpg 

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Visitor
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Registered: ‎06-29-2010

Re: 7-series ISERDES OVERSAMPLE bit order output

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Just went through this, easy to get it backwards.
Safe way is to simulate it. The models work great.
Even the IODELAYE2.
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Adventurer
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Registered: ‎02-08-2013

Re: 7-series ISERDES OVERSAMPLE bit order output

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I do have a simulation that works, but I found that when using networking mode for example, Q8 should be the lsb (or first sample) according to the datasheet, but when I chipscoped what appeared to work in simulation, I got the reverse in reality. This cast doubt for me on the simulation model.

 

Switching to OVERSAMPLE mode, the main problem was that I found contradictions in Xilinx whitepapers and datasheets as to wether the 90 deg offset clock should be connected to CLKB or OCLK. This wasn't helped by the fact that on the Xilinx dev board the FMC connector ties my ADC 1.8 LVDS lines to the HR 2.5 LVDS pins, so with that and other electrical properties logic high was being detected far shorter than expected!

 

I doubled my oversampling using a second data path offset by 45 deg and observed in chipscope and can confirm that for the ISERDES:

 

CLK and CLKB are your clk1 and inverted clk1 (or clk1 + 180 deg phase), and OCLK and OCLKB are clk1 + 90 deg phase, and clk1 + 180 deg phase.

 

Or to put another way:

 

Q1 is clocked in by CLK

Q2 is clocked in by OCLK

Q3 is clocked in by CLKB

Q4 is clocked in by OCLKB

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Visitor
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Registered: ‎06-29-2010

Re: 7-series ISERDES OVERSAMPLE bit order output

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I'm certain the sim model is correct. The flip between the OSERDES and the ISERDES a bit confusing.

 

Not sure how fast you are trying to go but it is really just a shift register at the end of the day. 

I was running 600 MHz as the GCLK and using a reference 75 MHz into the part, single ended data.

Didn't need to do bit by bit calibration. The bitslip stuff works great too. 

The white paper code makes it look a lot more complicated than it needs to be!

 

Sounds like you must be going real fast if you need clk90's!

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Adventurer
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Registered: ‎02-08-2013

Re: 7-series ISERDES OVERSAMPLE bit order output

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Nothing too fast, but I'm sampling 8-bit parallel data running at 250MHz DDR, so I need to deskew the lines as timing analysis showed that with my data eye size (taking into account jitter and skew) I couldn't guarantee sampling the correct data for all corners.

 

Due to the levels or electrical characteristics of the data signal, my known test pattern only shows high 1's for about 3ns instead of 4, which makes 4x oversampling useless. This is why I needed 8x oversampling to get a better (or higher resolution) view of the data edges!

 

From what I've read the bitslip feature of the SERDES makes the SERDES act as a shift register when used, but from the flip-flop diagrams in the SelectIO data sheet the outputs are acting like phase offset pipelined register chains, with each output it's own chain (in oversample mode anyway!).

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Registered: ‎06-29-2010

Re: 7-series ISERDES OVERSAMPLE bit order output

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Why not use the IDELAYE2 to find the transitions then offest it by a half period? 

I think that's the more conventional way to do this. 

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Registered: ‎02-08-2013

Re: 7-series ISERDES OVERSAMPLE bit order output

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That is what I'm doing - routing data bit from pad > IDELAY > ISERDES. Since my data is 250MHz DDR I have theoretical data periods of 2ns so need to oversample in order to see where the edge is with accuracy. In reality I'm finding the valid data window to be around 1 ns which is why I'm oversampling by 8.

 

Running a 250 MHz clock I don't fancy trying to run 1GHz+ sample clocks so use the OVERSAMPLE feature of the ISERDES with 2x 250MHz clocks offset by 90 deg, on 2 paths of the same data being offset by 45 deg! This gives me 8 samples about 500ps apart.

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Registered: ‎02-08-2013

Re: 7-series ISERDES OVERSAMPLE bit order output

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OK, I'm back with a testbench in hand. The testbanch is simple. There are 4 clocks in the design:

 

  • clk - 4ns period 
  • clk90 - 90 deg offset (1ns) of clk
  • clkn - 180 deg offset (2ns) of clk
  • clk90n - 270 deg offset (3ns) of clk

Naturally if oversampling a data bit, the clk edges should be sampling one after another in the order above. The design has 2 ISERDES components. The clock ports are connected as follows:

 

Setup1 (uut):

  • CLK = clk
  • CLKB = clkn
  • OCLK = clk90
  • OCLKB = clk90n
  • Q1 - Q4 = QL(0), QL(1), QL(2), QL(3)
  • Q5 - Q8 = QH(0), QH(1), QH(2), QH(3)

Setup2 (uut2):

  • CLK = clk
  • CLKB = clk90
  • OCLK = clkn
  • OCLKB = clk90n
  • Q1 - Q4 = Q2L(0), Q2L(1), Q2L(2), Q2L(3)
  • Q5 - Q8 = Q2H(0), Q2H(1), Q2H(2), Q2H(3)

 

I have a data bit as input to both SERDES and this bit alternates every 4ns. By default the data bit is offset 500ps to the clk signal, meaning a transition occurs after the first oversample bit. After 40 ns the data transition is shifted 1ns so it occurs between sample 2 and 3. Then shifted between sample 3 and 4, then after all samples.

 

We should expect to see an output pattern in the form of 1110/ 0001, 1100/ 0011, 1000/ 0111, 0000/ 1111 for each of the respective data offset periods being oversampled. The outputs seem to confirm that QL of setup 1 is meant to be the result of correct oversampling of the input, with the exception of the incorrect data output when the data transitions half way through the oversample period, between sample 2 and 3.

 

Is this a bug in the SERDES simulation model?

 

Below is the data transition 500ps after clk rising edge. Yellow marker is 1 cycle latency later, showing (correctly) the four samples (blue markers) of the data bit (red). Blue  maker to the right is the data offset period increasing.

 

ISERDES_500psOffset.jpg

 

Below is the data transition 1500ps after clk rising edge. Yellow marker is 1 cycle latency later, showing (incorrectly) the four samples (blue markers) of the data bit (red). The output is 0101. Blue maker to the right is the data offset period increasing.

 

ISERDES_1500psOffset.jpg

 

At 2500ps everything is correct again:

 

ISERDES_2500psOffset.jpg

 

Likewise for 3500ps, A-OK:

 

ISERDES_3500psOffset.jpg

 

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Adventurer
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Registered: ‎02-08-2013

Re: 7-series ISERDES OVERSAMPLE bit order output

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OK folks, it turns out the diagrams in the manual is correct:

 

CLK = CLK0

CLKB = CLK180 (or CLK0n)

OCLK = CLK90

OCLKB = CLK270 (or CLK90n)

 

Then:

 

Q1 = Sample 1

Q2 = Sample 3

Q3 = Sample 2

Q4 = Sample 4

 

This is how the testbench is behaving, and how it is implemented in the whitepaper Xapp523. Here is the diagram from the SelectIO datasheet:

 

ug471_OVERSAMPLE_diagram.jpg 

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Participant
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Registered: ‎10-17-2014

Re: 7-series ISERDES OVERSAMPLE bit order output

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I had a different problem with the ISERDES2 'Oversample' mode, see thread here: https://forums.xilinx.com/t5/7-Series-FPGAs/Understanding-ISERDES-Oversample-mode/m-p/751610/highlight/false#M20876

 

I am posting a reply in this thread, because I wanted to say that part of the accepted answer seems to be incorrect:

 

CLK = CLK0

CLKB = CLK180 (or CLK0n)

OCLK = CLK90

OCLKB = CLK270 (or CLK90n)

 

I have found that you must use the CLK0n and CLK90n option. If you use CLK180 and CLK270 generated by an MMCM, the oversampling does not seem to work properly in the real hardware (no problems in behavioral or timing simulation).

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Participant
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Registered: ‎09-11-2014

Re: 7-series ISERDES OVERSAMPLE bit order output

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This might be causing me problems in hardware.  (My sim works fine.)  When you say the oversampling does not work properly, do you remember any details about what you saw?

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