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Newbie igness
Newbie
6,044 Views
Registered: ‎03-14-2012

7 series SSTL2 support

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I have a need to interface a Kintex 7 to a 225MHz DDR SSTL2 device. (One direction only, with the FPGA being the DRIVER)

Can I even do this with a Series 7 device?

 

Looking through the datasheets, I don't see explicit support for SSTL2 (either type 1 or type2, although to be specific, I prefer to use type 1, but Im not against adding a few more termination resistors if it makes it all possible).

 

This would be in a HR bank, so I'm wondering what would happen if I just use a SSTL18 output buffer with VCCIO = 2.5, and Vtt = 1.25?

 

Or am I just out of luck?

 

Thanks.

 

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Voyager
Voyager
7,385 Views
Registered: ‎05-21-2008

Re: 7 series SSTL2 support

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If you want to use DDR1 anyway, try LVCMOS25 on HR bank and run a complete IBIS simulation. Add terminator if required to get good SI. This can be a workaround.

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Xilinx Employee
Xilinx Employee
5,988 Views
Registered: ‎03-18-2008

Re: 7 series SSTL2 support

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The best thing to do would be to simulate it using our IBIS models. We don't yet have IBIS models available for our 7-series devices. But you could get a good idea of what type of behavior to expect if you use our V-6 IBIS models. If the output driver meets your downstream input requirements you could be fine.

I don't know off hand how different SSTL2 is from SSTL18.
Xilinx Employee
Xilinx Employee
5,980 Views
Registered: ‎01-03-2008

Re: 7 series SSTL2 support

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There are significant difference in the IO construction in the 7 Series for both the HR and HP banks from all other FPGA families.  These changes were necessary to accomodate 2.5V and 3.3V IO in a 28nm process.

 

The SSTL_II 2.5V standard current requirements exceeded the what could be done within the design constraints and had to be eliminated.  Since there was very little expected need for supporting legacy DDR-SDRAM devices once the SSTL_II 2.5V support was removed the SSTL_I 2.5V went along with it resulting in no support for SSTL 2.5V.

 

>what would happen if I just use a SSTL18 output buffer with VCCIO = 2.5, and Vtt = 1.25?

 

Basically your design will not work if you attempt to do this.  The IOB configuration is different depending on if the IOSTANDARD is <1.8V or >2.5V.  If the bank senses that the voltage is in the 2.5V/3.3V range it will overide the configuration settings to protect the IO circuits.  These changes will then result in a partially functional I/O.

 

My suggestion is to jettison the DDR-SDRAM from your design and move to at least DDR2-SDRAM. 

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Voyager
Voyager
7,386 Views
Registered: ‎05-21-2008

Re: 7 series SSTL2 support

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If you want to use DDR1 anyway, try LVCMOS25 on HR bank and run a complete IBIS simulation. Add terminator if required to get good SI. This can be a workaround.

View solution in original post

Newbie igness
Newbie
5,934 Views
Registered: ‎03-14-2012

Re: 7 series SSTL2 support

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Thanks to everyone for the replies.

 

Very good info from all. (Especially interesting that the banks do I/O voltage sensing and corresponding self-protection)

 

As suggested, we've done an IBIS simulation using a LVCMOS2.5 driver and it looks like we're going to go that route.

 

Regards,

 

ig

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