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Registered: ‎11-24-2020

A few clarifications on SerDes


I would like to clarify a couple of doubts I have about SerDes

1. How is data protected and does this add to the latency

2. Why are there 2 clocks?


Thank you!


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Registered: ‎07-09-2009

As you have seen a lot of the FPGAs have high speed serial ports, 

     be this specific such as Ethernet , or more general such as the SerDes GTx ports.


Two clocks,

   I'm guessing that you are referring to the SerDes clock and the user clocks,

       The SerDes serial , runs at a constant clock frequency, with tight noise requirements as the Serial part is running constantly,

             The user data coming in is at a lower rate than the serial link can cope with. 


As for protection, 

    That is handled by the logic around the actual serial link,

        Its either part of the core, or its up to you to add. Depends what format your using.

Dos it add to the latency, 

    probably, depending upon the core chosen,


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Registered: ‎01-22-2015


There are generally two type of SERDES in Xilinx FPGAs.  One is called ISERDES and is a serial-to-parallel converter.  The other is called OSERDES and is a parallel-to-serial data converter.

For basic operation, consider a 1:8 Single-Data-Rate (SDR) ISERDES.  This device has a single input.  Data arrives at this input synchronously with an input clock called CLK.  So, ISERDES captures the input data on the rising-edges of CLK.

The 1:8 ISERDES also has 8 outputs. After 8 bits of data have been received at the ISERDES input, the 8 bits are send out of the 8 outputs synchronously with an output clock called CLKDIV.

For proper operation of the 1:8 SDR ISERDES, the frequency of CLK must be exactly 8x the frequency of CLKDIV.

The ISERDES automatically handles the crossing of data between the CLK-domain and CLKDIV-domain.

Typical there is latency equal to two cycles of CLKDIV for ISERDES.  

See UG471 for more information on ISERDES and OSERDES in 7-Series FPGAs.

Cheers, Mark

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