cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
758 Views
Registered: ‎10-10-2017

ADC Data LVDS Deserialization and Axi-Stream

Jump to solution

Hello,

the current task I have received is to interface a TI1443 Board to an Arty Z7-20 board.

The IWR1443 can be setup to work with DDR Clocks from 75 to 450 MHz, i.e. from 150 Mbps to 900 Mbps.

I have no previous experience, but a deep dive into these forums, finding quite a few similar requests.

The issue I currently have, is that my lead engineer wants to manage the rest of our project through an Axi-Stream protocol, so I was thinking about integrating the LVDS DDR SerDes unit inside an Axi-Stream wrapper, but I find the task a little daunting and heinous, and I am making no progress.

I have recently come to knowledge of SelectIO Interface Wizard, which seems like it should simplify my job.

The data that would come out of that block, as I understood, should just be a flow of the samples, reordered and with a known and given length, but absolutely not compliant to the AXI-Stream temporizations/flow/control, etc.

Should I implement an AxiS FIFO to store the data I am getting from the SelectIO, and then let my processor manage the reads from that FIFO and the passing of those samples to the rest of the elaboration chain?

We are interesting in saving "frames" of data to a RAM and then elaborating those data with typical FFT-style of math. We have a DMA involved, as should be typical

Otherwise, what's the link I am currently missing?

I imagine I should do:

IWR1443 -> LVDS Deserializer->FIFO <---> Axi-Stream Link <----> Processor <--->DMA<--->RAM

Thanks in advance, I hope @avrumw or @klumsde will save me ;)

1 Solution

Accepted Solutions
Highlighted
Scholar
Scholar
557 Views
Registered: ‎03-28-2016

Re: ADC Data LVDS Deserialization and Axi-Stream

Jump to solution

@cloudscraper-86,

I'm not so sure XAPP585 is going to be the best route to take.  I took a quick scan through the IWR1443 Data Sheet:

http://www.ti.com/lit/ds/swrs211c/swrs211c.pdf

On page 58, it states "The IWR1443 device uses MIPI D-PHY / CSI2-based format to transfer the raw A2D samples...". 

As such I would recommend that you look at Xilinx's MIPI CSI-2 Rx Subsystem:

https://www.xilinx.com/products/intellectual-property/ef-di-mipi-csi-rx.html

https://www.xilinx.com/support/documentation/ip_documentation/mipi_csi2_rx_subsystem/v4_1/pg232-mipi-csi2-rx.pdf

It requires a license, but you can get an eval liscense for any initial development work.

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com

View solution in original post

11 Replies
Highlighted
Teacher
Teacher
723 Views
Registered: ‎07-09-2009

Re: ADC Data LVDS Deserialization and Axi-Stream

Jump to solution

Can I suggest that you fess up to your head engineer that you need some pointers,

If not they might read it here first and not be impressed.

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
Highlighted
672 Views
Registered: ‎10-10-2017

Re: ADC Data LVDS Deserialization and Axi-Stream

Jump to solution

He has been informed before writing, and agreed, because this is something new for him, too

0 Kudos
Highlighted
Teacher
Teacher
652 Views
Registered: ‎07-09-2009

Re: ADC Data LVDS Deserialization and Axi-Stream

Jump to solution

Ok,

 

I dont know the TI1443 , 

 

I'd suggest you taek a standard engineering approac, and break the desing into parts.

As you suggets , first up is how to capture the data on the FPGA.

    You need to be able to receive the data reliably,

     I'd be asking questions like

           does data have an alligned clock with it,

          If so is th eclock continious or burst withthe data 

            You mention frames, how are the frames deliminated.

 

I'd go about making up a reciever block , probably based as you are doing, andput that into a ILA core in the FPGA,

     then you can prove your receivecircuit is relaible.

 

Second you have AXI.

    luckily, as your supervisor has said use that, thay must know all about AXI. 

So I'd read up on AXI, in particular streamed and packet modes,  and then formulate how  you would convert the data format you have received above into the format you need, 

Such things as, are you talkign to a processor, if so do you need interupts , or just polling of flags, what latency can you accept will all comeout of discusions on the many AXI options available.

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
Highlighted
Scholar
Scholar
626 Views
Registered: ‎03-28-2016

Re: ADC Data LVDS Deserialization and Axi-Stream

Jump to solution

If you are using LVDS serial streams to input the data from the ADC, you might want to look at the following XAPP:

https://www.xilinx.com/support/documentation/application_notes/xapp585-lvds-source-synch-serdes-clock-multiplication.pdf

This might give you somewhere to start.

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com
0 Kudos
Highlighted
601 Views
Registered: ‎10-10-2017

Re: ADC Data LVDS Deserialization and Axi-Stream

Jump to solution

hello @tedbooth and thanks for the support.


I have printed and read that note multiple times, but I find it a little too complex for my current level of understanding.

I think both you and the other contributer have correctly understood my issue: we just want to connect the radar board to our FPGA and interpret and re-order the samples from the ADC for usage in the rest of our chain.

IWR1443 uses DDR scheme, but, for example, i don't know if I should use the files suggested by the xapp585 (that I have already instantiated in my project) or the SelectIO peripheral from Xilinx's IP Library.

Assuming that I have correct information about the hw, and I am working with 900Mbps (450 MHz DDR clock) on 4 LVDS Data Lanes, is it correct that my top level Verilog code looks like this?

 

//////////////////////////////////////////////////////////////////////////////
//Device: 	7-Series
//Purpose:  	DDR top level receiver example - 1 channels of 4-bits each
//////////////////////////////////////////////////////////////////////////////

`timescale 1ps/1ps

module top5x2_7to1_ddr_rx (
input		reset,					// reset (active high)
input		refclkin,				// Reference clock for input delay control
input		clkin_p,  clkin_n,			// lvds channel 1 clock input
input	[3:0]	datain_p, datain_n,			// lvds channel 1 data inputs
output  [27:0]  rx_data
) ; 				

// Parameters

parameter integer     D = 4 ;				// Set the number of outputs per channel to be 5 in this example
parameter integer     N = 1 ;				// Set the number of channels to be 2 in this example



wire	[27:0]	rxd ;			
reg	[27:0]	old_rx	;				
wire		refclkint ; 		
wire		rx_mmcm_lckdps ;		
wire		rx_mmcm_lckdpsbs ;	
wire		rx_pixel_clk ;					
wire		delay_ready ;		
wire		rx_mmcm_lckd ;	

assign rx_data = old_rx;

// 200 or 300 Mhz Generator Clock Input

IBUF iob_200m_in(
	.I    			(refclkin),
	.O         		(refclkint));

BUFG bufg_200_ref (
	.I 			(refclkint), 
	.O 			(refclkintbufg)) ;
	
IDELAYCTRL icontrol (              			// Instantiate input delay control block
	.REFCLK			(refclkintbufg),
	.RST			(reset),
	.RDY			(delay_ready));

	
n_x_serdes_1_to_7_mmcm_idelay_ddr #(
	.N			(1),
	.SAMPL_CLOCK		("BUFIO"),
	.INTER_CLOCK		("BUF_R"),
	.PIXEL_CLOCK		("BUF_G"),
	.USE_PLL		("FALSE"),
 	.HIGH_PERFORMANCE_MODE 	("FALSE"),
      	.D			(D),				// Number of data lines
      	.REF_FREQ		(200.0),			// Set idelay control reference frequency
      	.CLKIN_PERIOD		(1.111),			// Set input clock period
      	.MMCM_MODE		(1),				// Parameter to set multiplier for MMCM to get VCO in correct operating range. 1 multiplies input clock by 7, 2 multiplies clock by 14, etc
	.DIFF_TERM		("TRUE"),
	.DATA_FORMAT 		("PER_CLOCK"))  		// PER_CLOCK or PER_CHANL data formatting
rx0 (                      
	.clkin_p   		(clkin_p),
	.clkin_n   		(clkin_n),
	.datain_p     		(datain_p),
	.datain_n     		(datain_n),
	.enable_phase_detector	(1'b1),				// enable phase detector operation
	.enable_monitor		(1'b0),				// enables data eye monitoring
	.dcd_correct		(1'b0),				// enables clock duty cycle correction
	.rxclk    		(),
	.rxclk_d4    		(),				// intermediate clock, use with data monitoring logic
	.idelay_rdy		(delay_ready),
	.pixel_clk		(rx_pixel_clk),
	.reset     		(reset),
	.rx_mmcm_lckd		(rx_mmcm_lckd),
	.rx_mmcm_lckdps		(rx_mmcm_lckdps),
	.rx_mmcm_lckdpsbs	(rx_mmcm_lckdpsbs),
	.clk_data  		(),
	.rx_data		(rxd),
//	.bit_rate_value		(16'h1050),			// required bit rate value in BCD
	
	.bit_rate_value		(16'h0900),			// required bit rate value in BCD - 900 Mbps
	.bit_time_value		(),
	.status			(),
	.eye_info		(),				// data eye monitor per line
	.m_delay_1hot		(),				// sample point monitor per line
	.debug			()) ;				// debug bus

    always @(posedge rx_pixel_clk) begin
        old_rx <= rxd ;
    
    end
      	
endmodule

This unit would output 28 bit data, but I am missing temporization and the internal configuration of the samples, which should depend from my radar.

Would it be a decent approach to use a FIFO as temporary storage for these data, and then output the data from the FIFO with an axi-stream interface to connect it to my DMA and the rest of the project?

0 Kudos
Highlighted
Teacher
Teacher
590 Views
Registered: ‎07-09-2009

Re: ADC Data LVDS Deserialization and Axi-Stream

Jump to solution

Yes

but DMAing might be easier form a lump of memmory to another lump.

Read up on how DMA might work, look in particular at scatter gather approaches.

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
Highlighted
Scholar
Scholar
558 Views
Registered: ‎03-28-2016

Re: ADC Data LVDS Deserialization and Axi-Stream

Jump to solution

@cloudscraper-86,

I'm not so sure XAPP585 is going to be the best route to take.  I took a quick scan through the IWR1443 Data Sheet:

http://www.ti.com/lit/ds/swrs211c/swrs211c.pdf

On page 58, it states "The IWR1443 device uses MIPI D-PHY / CSI2-based format to transfer the raw A2D samples...". 

As such I would recommend that you look at Xilinx's MIPI CSI-2 Rx Subsystem:

https://www.xilinx.com/products/intellectual-property/ef-di-mipi-csi-rx.html

https://www.xilinx.com/support/documentation/ip_documentation/mipi_csi2_rx_subsystem/v4_1/pg232-mipi-csi2-rx.pdf

It requires a license, but you can get an eval liscense for any initial development work.

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com

View solution in original post

Highlighted
504 Views
Registered: ‎10-10-2017

Re: ADC Data LVDS Deserialization and Axi-Stream

Jump to solution

@tedbooth Hello and thanks for your explanation. It must (might?) be an oversight by my lead engineer, which is frankly quite plausible.

Just for clarity, I would like to recap what I have understood.

Since my source radar is sending data through another interface (CSI-2 Format), I should :

1. find the pins from radar's board mapped to CSI-2 signals, as in page 13 of Texas Instruments' datasheet

2. instantiate the CSI2 Receiver, as needed and as explained in its proper manual that you suggested

3. the unit outputs Axi-Stream data intrinsically so I do not have to add another layer of hierarchy, like an Axi Wrapper

4. I can connect the output of this interface to the microcontroller and the DMA as usual, in a typical axi master/slave fashion

Did i miss anything major?


I would also like to deeply thank you for your kindness.

0 Kudos
Highlighted
Scholar
Scholar
481 Views
Registered: ‎03-28-2016

Re: ADC Data LVDS Deserialization and Axi-Stream

Jump to solution

@cloudscraper-86 

I think you are on the right track.  I don't see any glaring omissions.

There are likely some example design using the CSI-2 Rx that you can look at for reference.  Do a search on Xilinx.com.

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com
Highlighted
450 Views
Registered: ‎10-10-2017

Re: ADC Data LVDS Deserialization and Axi-Stream (CSI-2?)

Jump to solution

hello @tedbooth , i am building the project in Vivado and I should be pretty good to go, but I have a question that I cannot seem to clarify on manuals or on the web

 

The CSI-2 RX subsystem has two sets of clock ports and data ports, one for High Speed and one for Low Power mode. On page 50 of the IWR1443 datasheet it says "the HS to LP transition of the CLK does not actually take place since the CLK is always ON in HS mode".


Does it mean that I should physically connect ONLY the 4 differential HS pins for the data plus only the differential HS clock, because the other operating mode is not actually in use?


Thanks again,

kindest regards,

Michele Marconi

0 Kudos
Highlighted
Scholar
Scholar
435 Views
Registered: ‎03-28-2016

Re: ADC Data LVDS Deserialization and Axi-Stream (CSI-2?)

Jump to solution

@cloudscraper-86 

From the descrition that you provided, that's how I would interpret the operation of the device.

I haven't used the CSI-2 Subsystem in a design, but that's how I would hook it up in this case.

You might want to submit a new question to the forum for the CSI-2 Subsystem.

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com