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Registered: ‎02-19-2019

ADC parallel LVDS interface

Hi everyone,

 have a project that collects all data from ADC (ADS4249 - 14 bits LVDS - 2 channels - 60 MHz) and saves it to a FIFO (Xilinx FPGA kintex 7 connected to DDR3) then sends this data to FX2LP ( 48 MHz) when required.

I performed read / write to the ADC registers and ran properly (writing and reading back).

I have referenced this link to generate data received from the ADC interface (I use the system clock 200 MHz, ADC 60 MHz) (please see ADCInterface.sv). I configured the registers to have a test pattern at the ADC output, but I couldn't get what I hoped for. (Example: (image in attachment): we have configured to read 0x2AAA again (10 1010 1010 1010), we have received 0x2A81 (10 1010 1000 0001)).

I attached the design and below is timing constraints:

 

#virtual clock driving data from ADC
create_clock -period 16.667 -name ADC_Data_Clk 

#Actual 90 degree shifted bit clock from ADC
create_clock -period 16.667 -name ADCBITCLK -waveform {12.5 20.833} [get_ports ADC_CLKOUT_P]

set_clock_groups -asynchronous -group [get_clocks ADCBITCLK] -group [get_clocks ADC_Data_Clk]

set_false_path -setup -fall_from [get_clocks ADC_Data_Clk] -rise_to [get_clocks ADCBITCLK]
set_false_path -setup -rise_from [get_clocks ADC_Data_Clk] -fall_to [get_clocks ADCBITCLK]
set_false_path -hold -fall_from [get_clocks ADC_Data_Clk] -rise_to [get_clocks ADCBITCLK]
set_false_path -hold -rise_from [get_clocks ADC_Data_Clk] -fall_to [get_clocks ADCBITCLK]

set_input_delay -clock [get_clocks ADC_Data_Clk] -max 4.07 [get_ports {TOP_ADC_LVDS_AP[*]* BOT_ADC_LVDS_BP[*]*}]
set_input_delay -clock [get_clocks ADC_Data_Clk] -max 4.07 [get_ports {TOP_ADC_LVDS_AP[*]* BOT_ADC_LVDS_BP[*]*}] -clock_fall -add_delay
set_input_delay -clock [get_clocks ADC_Data_Clk] -min -4.34 [get_ports {TOP_ADC_LVDS_AP[*]* BOT_ADC_LVDS_BP[*]*}] -add_delay
set_input_delay -clock [get_clocks ADC_Data_Clk] -min -4.34 [get_ports {TOP_ADC_LVDS_AP[*]* BOT_ADC_LVDS_BP[*]*}] -add_delay -clock_fall

 

Please help me point out what I am wrong here (the design or timing?)!

Thank you very much!

 

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