have a project that collects all data from ADC (ADS4249 - 14 bits LVDS - 2 channels - 60 MHz) and saves it to a FIFO (Xilinx FPGA kintex 7 connected to DDR3) then sends this data to FX2LP ( 48 MHz) when required.
I performed read / write to the ADC registers and ran properly (writing and reading back).
I have referenced this link to generate data received from the ADC interface (I use the system clock 200 MHz, ADC 60 MHz) (please see ADCInterface.sv). I configured the registers to have a test pattern at the ADC output, but I couldn't get what I hoped for. (Example: (image in attachment): we have configured to read 0x2AAA again (10 1010 1010 1010), we have received 0x2A81 (10 1010 1000 0001)).
I attached the design and below is timing constraints: