07-27-2018 01:14 AM
Iam currently designing a board with the Artix 35T.
I want to power all banks (only HR) with 3.3V.
The system clock I want to use is a 3.3V 100MHz LVDS generated by a SI5338 clockgenerator.
Is this possible? If I understand this correct this should work.
I have read, that I can connect a 3.3 LVDS singal to a 3.3V powered HR Bank.
The requirement is to place an external 100 Ohm termination resistor an disable internal termination.
07-27-2018 01:38 AM
@tobir You are right about using external termination and disabling internal termination. You also need to check the Vin specs.
Check this AR and follow the flow chart for the HR banks https://www.xilinx.com/support/answers/43989.html
07-27-2018 01:54 AM
thanks for the fast replay.
The clock generator has the following specs.:
VOC: 1.125 (min) 1.2 (typ) 1.275 (max) -V
VSEPP (VOD): 0.25 (min) 0.35 (typ) 0.45(max) - Vpp
If I understand this correct we are in the range that we can use the 100 ohm termination only.
1.2V + 0.35/2 < 3.3V+0.2V
07-27-2018 02:14 AM
@tobir Yeah, you need only the 100 ohm external termination.
07-27-2018 04:48 AM
one last question ;).
At the AC701 Evaluation Board does the Si570 (U34) provide a 3.3V LVDS signal?
Iam asking because the LVDS signals goes to Bank 14 which is powerd by 3.3V without any termination.
I gues the 100 ohm termination is at the Si570,