cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
nekster
Visitor
Visitor
267 Views
Registered: ‎12-03-2018

ARTIX-7, LVDS-2.5 on board

Hello, i'm designing a board with LVDS-2.5 interconnection between two Artix-7. I don't understand fully, how to equalize lengths of the diff pairs nets. This is about delays, but i don't know, how to calculate. May be you can give any formula to do it. 

Thank you in advance

0 Kudos
2 Replies
drjohnsmith
Teacher
Teacher
244 Views
Registered: ‎07-09-2009

delay is basically down to track length

so you measure and make certain the track length on the _P and the _N are "the same" within a certain length, 

  

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
joancab
Teacher
Teacher
236 Views
Registered: ‎05-11-2015

Differential lines rise and fall at the same time at the transmitter and, when the lengths are the same, also at the receiver. If there is a length mismatch, they will still cross each other but not at V/2 what can cause problems. Many PCB CAD packages do a physical length calculation for you. But... to be rigorous, signal delay depends on trace shape and environment, so not every 1 cm trace delays the same. The best is you look at equal electrical length (delay), some advanced CAD packages do that. What happens with differential pairs is that because the lines run parallel to each other, they have very similar characteristics and their electrical lengths are proportional to their physical lengths, so you can, in practice, trust physical length in the case of differential pairs. You can typically match lengths to less than a mm by adding small meanders (accordions) here and there. From my experience, with frequencies in the GHz, you even need to compensate phases after a 45 degree turn because the outer trace is longer than the inner so a small bump is added. This is not exactly 'length matching' but keeping the signals precisely 180 degrees out of phase. 

There is another need with diff. pairs, length match between pairs. In this case, because the routing can be very different from pair to pair, just the physical length can be very misleading, and either electrical length calculation is needed or, if you are lucky enough, trust physical length match, route them as similar to each other as possible (in terms of layer changes, accordions, etc) and use the delay adjustment capabilities of the FPGA.

If your question is about absolute delays (time) you should use the propagation speed (not the speed of light), that depends on PCB materials, etc. Again, some tools calculate that if you provide the PCB details or else you can use some rule of thumb as a guess. Have a look at this: Saturn PCB Toolkit - Saturn PCB Design | Saturn PCB Design

0 Kudos