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Newbie
Newbie
3,903 Views
Registered: ‎08-06-2015

ARTIX7 IBIS model

We have done simulation for clock signal using SSTIL1.5_S_HR model from ARTIX-7 & capatured results at the 100E load.I am attaching simulation results for your reference which is not proper.


when we checked rising waveform of SSTIL1.5_S_HR buffer we found that , till 1.25ns the signal is rising i.e 1 bit period(1.25 ns) of our simulating frequency 400 MHz.

hence we are suspecting problem in IBIS model of ARTIX-7.

 

if anybody gone through such problem please provide your suggestion.

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Scholar
Scholar
3,826 Views
Registered: ‎02-27-2008

Re: ARTIX7 IBIS model

Slow down the clock.


It is perhaps 2 to 3X times too fast.

 

The clock is just too fast for this IO standard and possibly for the device itself.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Xilinx Employee
Xilinx Employee
3,818 Views
Registered: ‎01-03-2008

Re: ARTIX7 IBIS model

It isn't clear to me how your simulation was setup.  You said that you captured the "results at the 100E load".  Looking at the waveform it appears that you may have connected the end of the transmission line with a 100ohm resistor to ground.  If this is correct it would explain the waveform as this is not the correct termination for a SSTL 1.5V signal.

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