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Explorer
Explorer
5,655 Views
Registered: ‎11-27-2016

AURORA 64B66B

Hello,

           I am using AURORA 64B66B fo SFP in K7  board(it is for Receiver)..  I am following xapp1212-simplx ..and not clear about  the following(Default from Aurora),

set_property LOC AG14 [get_ports RX_HARD_ERR] 

set_property IOSTANDARD LVCMOS18 [get_ports RX_HARD_ERR] 

As per my board how to choose this pin and corresponding PIN

My  FPGA: xc7k160tffg676  High Range(HR Type)

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Community Manager
Community Manager
5,606 Views
Registered: ‎07-23-2012

You can assign this to any pin of your choice on your board. If you don't have LEDs on your custom board, you can connect this port to a VIO to monitor it's state.

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Explorer
Explorer
5,597 Views
Registered: ‎11-27-2016

Thanks for your response,

   How to connect this to VIO, I am not aware about this

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Xilinx Employee
Xilinx Employee
5,580 Views
Registered: ‎02-14-2014

Hello abinaya1991@,

 

In order to be familiar with VIO core, you can follow steps in below tutorial -

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_4/ug936-vivado-tutorial-programming-debugging.pdf

Regards,
Ashish
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Community Manager
Community Manager
5,566 Views
Registered: ‎07-23-2012

You can check Vivado Lab Tools in Aurora IP customization GUI as shown below to include ILA and VIO cores in the design.

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Explorer
Explorer
5,541 Views
Registered: ‎11-27-2016

So, 

      Don't we need to assign the pin in XDC? Shall I remove this line in xdc? 

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Moderator
Moderator
5,478 Views
Registered: ‎02-16-2010

If you are monitoring RX_HARD_ERR using VIO, you can remove the LOC constraint in .xdc file
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Explorer
Explorer
5,452 Views
Registered: ‎11-27-2016

Hi,

     After adding the VIO IP in our Aurora example design, How to connect the specification to VIO? 

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Moderator
Moderator
5,178 Views
Registered: ‎02-16-2010

Please generate IP with "vivado lab tools" option and generate IP example design. You can refer to example code in IP example_design file to know how to use VIO.

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