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Visitor
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Registered: ‎04-29-2019

About Kintex7 VCCAUX Voltage Loss

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Hi,

I'm using Kintex7 XC7K325T-1FFG676I in my design. When I performed low temperature tests around -30 degree centigrade, VCCAUX voltage was shorted to GND because of the VCCAUX regulator. At that time, just proper VCCINT voltage was exist and VCCO voltages were disabled by following the VCCAUX voltage loss. So we had just VCCINT voltage and what would be when we give just the VCCINT voltage of Kintex7 device? Should we expect any problem something like FPGA burn? 

When I searched the datasheet I couldn't see any information about loss of one of the mandatory voltages. Do you have any information about this case?

Regards,

Dogancan

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-07-2018

Hello @ndaksu 

Based on your inputs, I suspect following are the possible causes for FPGA damage on your board:

  1. Based on your input, there are separate regulator for VCCAUX and VCCO. Failure of VCCAUX might have caused violation of condition provided in DS182 (v2.18) : “Voltage difference between VCCO of HR bank and VCCAUX must not exceed 2.625V for longer than TVCCO2VCCAUX for each power-on/off cycle.” Violation of this condition can cause damage of FPGA fabric.
  2. When VCCO is absent and FPGA pins are driven by external devices connected to FPGA IO, this condition can cause forward biasing of clamp diode present at FPGA IO’s. Overdriving this clamp diode more than IIN specification provided in DS182 (v2.18) can cause damage FPGA IO sites and related regions.
  3. As per UG907 (v2019.2): Table 1-1: FPGA Resources and the Power Supply, VCCAUX and VCCAUX_IO power rail handles Clock Managers (MMCM, PLL, etc.), IODELAY/IDELAYCTRL, All output buffers, Differential Input buffers, VREF-based, single-ended I/O standards,  Phaser. These resources act as bridge between FPGA fabric resources powered by VCCINT. So, it is possible that mishap on VCCAUX power rails can cause damage of FPGA fabric.

 

Please note FPGA damage can happen anywhere on FPGA fabric, IO’s regardless to any particular FPGA power rail failure or over-driving. Reason is FPGA resources are interconnected to each other internally and sometimes power supplies on FPGA board are shared externally to use regulator on board efficiently . So, even though there are separate power rails for various FPGA resources, it is possible calamity in power of VCCAUX can cause damage in FPGA fabric and VCCINT.

Regards,
Bhushan

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Moderator
Moderator
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Registered: ‎09-18-2014

What do you mean by "FPGA burn" that you sound to be concerned about? Assuming VCCO was lost first then loosing VCCAUX is in natural and recommended sequence for an power down. With 7-series the only thing really to be concerned about is the TVCCO2VCCAUX rule which is documented well in the Kintex-7 data sheet ds182. Other then that I would also note that without VCCO the IO banks are left without much ESD protection. Also voltage on the IO pins should track VCCO as well if possible to limit current drain. 

 

Regards,

T

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Visitor
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Registered: ‎04-29-2019

Hi,

Let me explain our situation in detail. I am aware of power-on and power-off sequences of Kintex7 device and our situation isn't a proper power down sequence.  As I wrote in my previous message, we first lost VCCAUX and then our voltage monitoring circuit turned off the VCCO voltages. Actually, VCCAUX voltage was shorted to ground and VCCO voltages became float because VCCO regulators was turned off due to VCCAUX voltage loss. So, this case is not same as the power-down sequence because we first lost VCCAUX voltage. By the way, we had just VCCINT voltage and our FPGA had been properly programmed. 

When I saw this short circuit situation, I terminated the low temperature test and then tried to debug our problem. After that, I disassembled the external connections of Kintex7 that includes all point-of-load connections. So, we clearly saw that VCCINT voltage was shorted to ground over the Kintex7 device. Until now, this was our case and now I'll explain our doubts.

Actually, we suspect that the permanent VCCAUX voltage loss due to VCCAUX voltage regulator (there weren't short circuits between VCCAUX and GND pins of FPGA, this was the problem of VCCAUX voltage regulator) might have caused to short circuit or any damage on the internal core voltage (VCCINT) circuitry. Hence, the VCCINT was shorted to ground. We just want to learn whether it is possible or not. If it is possible we will try to prevent permanent mandatory voltage loss in the our next designs. 

Also I mean from the "FPGA burn" that a permanent damage in FPGA logic or internal power distribution circuitry. 

I hope everything is clear now.

Regards,

Dogancan

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Xilinx Employee
Xilinx Employee
221 Views
Registered: ‎03-07-2018

Hello @ndaksu 

Based on your inputs, I suspect following are the possible causes for FPGA damage on your board:

  1. Based on your input, there are separate regulator for VCCAUX and VCCO. Failure of VCCAUX might have caused violation of condition provided in DS182 (v2.18) : “Voltage difference between VCCO of HR bank and VCCAUX must not exceed 2.625V for longer than TVCCO2VCCAUX for each power-on/off cycle.” Violation of this condition can cause damage of FPGA fabric.
  2. When VCCO is absent and FPGA pins are driven by external devices connected to FPGA IO, this condition can cause forward biasing of clamp diode present at FPGA IO’s. Overdriving this clamp diode more than IIN specification provided in DS182 (v2.18) can cause damage FPGA IO sites and related regions.
  3. As per UG907 (v2019.2): Table 1-1: FPGA Resources and the Power Supply, VCCAUX and VCCAUX_IO power rail handles Clock Managers (MMCM, PLL, etc.), IODELAY/IDELAYCTRL, All output buffers, Differential Input buffers, VREF-based, single-ended I/O standards,  Phaser. These resources act as bridge between FPGA fabric resources powered by VCCINT. So, it is possible that mishap on VCCAUX power rails can cause damage of FPGA fabric.

 

Please note FPGA damage can happen anywhere on FPGA fabric, IO’s regardless to any particular FPGA power rail failure or over-driving. Reason is FPGA resources are interconnected to each other internally and sometimes power supplies on FPGA board are shared externally to use regulator on board efficiently . So, even though there are separate power rails for various FPGA resources, it is possible calamity in power of VCCAUX can cause damage in FPGA fabric and VCCINT.

Regards,
Bhushan

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Give Kudos to a post which you think is helpful and reply oriented.
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Visitor
Visitor
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Registered: ‎04-29-2019

Hello Bhushan,

Thank you for your reply. I reviewed our design by considering your cases. Actually, first case wouldn't be possible for our design because our voltage monitoring circuitry turns-off the VCCO voltages 20 us after the VCCAUX loss. It is quite enough to achieve the DS182 (v2.18) : “Voltage difference between VCCO of HR bank and VCCAUX must not exceed 2.625V for longer than TVCCO2VCCAUX for each power-on/off cycle.”  requirement. 

Second case might be possible but VCCINT voltage shorted to ground over the FPGA as I said before. So, I couldn't check whether the I/O banks were damaged or not.

Third case might also be possible and honestly it is the best possible case in my opinion. However, I cannot try this case again because I don't want to damage another FPGA   

Finally, we will think about third case and maybe we should use a short circuit protection circuit between point-of-load and FPGA's voltage pins. 

Best Regards,

Dogancan