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chao_xilinx
Visitor
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Registered: ‎01-23-2019

About LCD display in kc705

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I was trying to write some verilog code to drive the LCD display.

However, I realized that our data[3:0] is not connected. For the examples I studied, they all have [7:0] data bus for each character.

How can I work out this? Do you have some working sample code for kc705 FPGA?

Thanks!

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andresb
Xilinx Employee
Xilinx Employee
1,220 Views
Registered: ‎06-21-2018

Hi,

If you search online for "16x2 LCD HDL", you'll find example code.
I found one on Opencores written in VHDL that is well documented and this subset written in Verilog:
https://www.quora.com/What-is-the-Verilog-code-to-display-a-character-on-an-LCD-screen-of-the-Spartan-3E-XC3S400-FPGA-kit

KC705 has a 7 pin interface to it. From the XDC file:

 Line 812: set_property PACKAGE_PIN Y11 [get_ports LCD_RS_LS]
 Line 813: set_property IOSTANDARD LVCMOS15 [get_ports LCD_RS_LS]
 Line 814: set_property PACKAGE_PIN Y10 [get_ports LCD_DB7_LS]
 Line 815: set_property IOSTANDARD LVCMOS15 [get_ports LCD_DB7_LS]
 Line 816: set_property PACKAGE_PIN AA11 [get_ports LCD_DB6_LS]
 Line 817: set_property IOSTANDARD LVCMOS15 [get_ports LCD_DB6_LS]
 Line 818: set_property PACKAGE_PIN AA10 [get_ports LCD_DB5_LS]
 Line 819: set_property IOSTANDARD LVCMOS15 [get_ports LCD_DB5_LS]
 Line 820: set_property PACKAGE_PIN AA13 [get_ports LCD_DB4_LS]
 Line 821: set_property IOSTANDARD LVCMOS15 [get_ports LCD_DB4_LS]
 Line 822: set_property PACKAGE_PIN AB13 [get_ports LCD_RW_LS]
 Line 823: set_property IOSTANDARD LVCMOS15 [get_ports LCD_RW_LS]
 Line 824: set_property PACKAGE_PIN AB10 [get_ports LCD_E_LS]
 Line 825: set_property IOSTANDARD LVCMOS15 [get_ports LCD_E_LS]

Thanks,
Andres

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andresb
Xilinx Employee
Xilinx Employee
1,221 Views
Registered: ‎06-21-2018

Hi,

If you search online for "16x2 LCD HDL", you'll find example code.
I found one on Opencores written in VHDL that is well documented and this subset written in Verilog:
https://www.quora.com/What-is-the-Verilog-code-to-display-a-character-on-an-LCD-screen-of-the-Spartan-3E-XC3S400-FPGA-kit

KC705 has a 7 pin interface to it. From the XDC file:

 Line 812: set_property PACKAGE_PIN Y11 [get_ports LCD_RS_LS]
 Line 813: set_property IOSTANDARD LVCMOS15 [get_ports LCD_RS_LS]
 Line 814: set_property PACKAGE_PIN Y10 [get_ports LCD_DB7_LS]
 Line 815: set_property IOSTANDARD LVCMOS15 [get_ports LCD_DB7_LS]
 Line 816: set_property PACKAGE_PIN AA11 [get_ports LCD_DB6_LS]
 Line 817: set_property IOSTANDARD LVCMOS15 [get_ports LCD_DB6_LS]
 Line 818: set_property PACKAGE_PIN AA10 [get_ports LCD_DB5_LS]
 Line 819: set_property IOSTANDARD LVCMOS15 [get_ports LCD_DB5_LS]
 Line 820: set_property PACKAGE_PIN AA13 [get_ports LCD_DB4_LS]
 Line 821: set_property IOSTANDARD LVCMOS15 [get_ports LCD_DB4_LS]
 Line 822: set_property PACKAGE_PIN AB13 [get_ports LCD_RW_LS]
 Line 823: set_property IOSTANDARD LVCMOS15 [get_ports LCD_RW_LS]
 Line 824: set_property PACKAGE_PIN AB10 [get_ports LCD_E_LS]
 Line 825: set_property IOSTANDARD LVCMOS15 [get_ports LCD_E_LS]

Thanks,
Andres

View solution in original post

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mager_swind
Visitor
Visitor
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Registered: ‎04-11-2021
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andresb
Xilinx Employee
Xilinx Employee
294 Views
Registered: ‎06-21-2018

Hi @mager_swind, the Quora site still works for me.

This is the code:

`timescale 1ns / 1ps 
////////////////////////////////////////////////////////////////////////////////// 
 
////////////////////////////////////////////////////////////////////////////////// 
module keyboard(clk,data,sel,seg,parity,stop ); 
input clk; 
input  data; 
output reg [3:0]  sel; 
output  [6:0] seg; 
output  reg parity,stop; 
reg [3:0]i=0; 
 
reg [7:0] out=0,a=0; 
 
reg z=1'b1; 
always@(posedge clk) 
begin  
			case(i) 
			0   : begin z=data;	end				 
			1  : a[0]=data; 
			2  : a[1]=data; 
			3  : a[2]=data; 
			4  : a[3]=data; 
			5  : a[4]=data; 
			6  : a[5]=data; 
			7  : a[6]=data; 
			8  : a[7]=data; 
			9  : parity=data; 
			10  : stop=data; 
			endcase 
			if(z!=0) 
			begin 
				i=0; 
				end 
				else 
				begin 
			i=i+1'b1; 
			end 
		out=a; 
end 
 
reg [6:0]tt=0; 
					 
		always @(out) 
		begin 
		sel=4'b1110; 
		case(out) 
		8'h1c : tt=7'b0001000; //A=1c; 
		8'h1b : tt=7'b0100100; //S=1b; 
		8'h16 : tt=7'b1001111; // 1=16 
		8'h1e : tt=7'b0010010; // 2=1E 
		8'h26 : tt=7'b0000110; // 3=26 
		8'h25 : tt=7'b1001100; // 4=25 
		8'h2e : tt=7'b0100100; // 5=2e 
		8'h36 : tt=7'b0100000; // 6=36 
		8'h3d : tt=7'b0001111; // 7=3d 
		8'h3e : tt=7'b0000000; // 8=3e 
		8'h46 : tt=7'b0001100; // 9=46 
		8'h45 : tt=7'b0000001; // 0=45 
		 
		default : tt=7'b1111110;  
		endcase 
		end 
	assign seg=tt; 
endmodule 
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