01-19-2019 05:59 AM
01-19-2019 06:15 PM
So you're saying you dug up an old 2013.1 version of Vivado and exported IBIS models from it--and the labels in that export don't match the ones listed in the AR? Because Vivado 2013.1 is the version that's covered by that AR.
IBIS models and their labels seem to be constantly changing across versions of Vivado. Between two DDR4 interfaces from one part/instance of a Zynq MPSoC (exported in 17.4) and another part/instance (exported in 18.2), our SI guy found differences in the names and behaviors of the models for the same exact interface pins.
I wouldn't get hung-up on model labels. Just use the latest version of Vivado to export the latest (and hopefully, most accurate) IBIS models.
01-20-2019 02:30 AM - edited 01-20-2019 02:32 AM
I'm new to Xilinx's products. Sometimes, I feel Xilinx's product's are not documented so well. In UG471 (v1.10) May 8, 2018, it also states:
Although the optimal drive and termination scheme for any new design is determined through careful signal-integrity analysis, initial considerations include:
• HP I/O banks: SSTL15_T_DCI at the 7 series FPGAs bidirectional pins (DQ and DQS), and SSTL15 at the unidirectional pins (all other pins). ODT used at the memory device on the bidirectional signals, and external parallel-termination resistors to VTT = VCCO/2 for the unidirectional signals.
See, it's a doc just 7 months ago. So, I doubt if I do something wrong when export the model.