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Anonymous
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Adjustable Clock Delay with min 10ps delay

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Hi,

 

I am working on a project that requires generating a square wave with adjustable frequency(2Mhz,4Mhz,8Mhz,16Mhz,32Mhz and 64Mhz) with adjustable delay (+/- 5ns with 0.01 ns setps=> 0.01, 0.02, 0.03.....5ns). I have an Artix-7 FPGA with a 100Mhz clock for testing.

 

The user has the option to select the frequency (min 2Mhz and Max 64Mhz) and the amount of delay (min 0.01ns and max 5ns).

 

I didn't find any problems getting the adjustable frequency which is by either using Clock wizard or simple clock divider.

 

What I am having a problem is getting the adjustable delay. I tired phase shift, but still getting min. 0.01ns (10ps) delay is not possible for lower frequency (2Mhz, 4Mhz and so on).

 

I am just wondering if it is practically possible to have a variable delay- min. 10ps or (0.01ns) to max. 5ns delay for the frequency range from 2Mhz to 64 Mhz????  Can this be done in FPGA (any FPGA)?

 

If it is possible then I wanted to know how and which family of FPGA would be best to test this idea?

 

Thanks,

Deepak

 

 

 

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Scholar
Scholar
6,868 Views
Registered: ‎02-27-2008

Re: Adjustable Clock Delay with min 10ps delay

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d,

 

Even with the earlier DCM, the minimum phase step was 1/256 of a period, or ~ 35 ps, whichever is larger.

 

I do not think this has changed.

 

Best case phase matching between elements in the clock trees is +/- 100 ps from process variations.  Calibration (for DDR MIG) adapts for these variations to the best of the phase shifting abilities, but that isn't as fine as you would like.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

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Scholar
Scholar
6,869 Views
Registered: ‎02-27-2008

Re: Adjustable Clock Delay with min 10ps delay

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d,

 

Even with the earlier DCM, the minimum phase step was 1/256 of a period, or ~ 35 ps, whichever is larger.

 

I do not think this has changed.

 

Best case phase matching between elements in the clock trees is +/- 100 ps from process variations.  Calibration (for DDR MIG) adapts for these variations to the best of the phase shifting abilities, but that isn't as fine as you would like.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

View solution in original post

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Teacher
Teacher
3,726 Views
Registered: ‎03-31-2012

Re: Adjustable Clock Delay with min 10ps delay

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@Anonymous I believe ultrascale delay elements can do better but haven't tried myself yet.

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