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lis_user1
Explorer
Explorer
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Registered: ‎11-17-2015

Are FCLK_CLK0/1/2 considered synchronous?

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Hi, 

 

When the ZYNQ CPU generates three fabric clocks, FCLK0/1/2 from the IO_PLL, at 50/100/200MHz. May I consider them synchronous? 

 

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smarell
Community Manager
Community Manager
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Registered: ‎07-23-2012
The four fabric clocks (FCLK) are derived from individually selected PLLs in the PS. Hence, you can't assume them to be synchronous.

Do you have any specific requirement to use synchronous clocks (of different frequencies) in your design? If this is the case, why don't you use a single FCLK (say FCLK0) and drive to a MMCM/PLL on PL to derive synchronous clocks.
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ronnywebers
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Registered: ‎10-10-2014

@balkris :  is this really the case? I've found this in the TRM section 2.7.1 Clocks & Resets, so I'm confused now ... 

 

Clocks
The PS clock module provides four frequency-programmable clocks (FCLKs) to the PL that are
physically spread out along the PS–PL boundary. The clocks can also be individually controlled. The
FCLK clocks can be routed to PL clock buffers to serve as a frequency source.
Note: There is no guaranteed timing relationship between any of the four PL clocks and between
any of the other PS-PL signals. Each clock is independently programmed and operated. The
FCLKCLKTRIGN[3:0] signals are currently not supported. They must be tied to ground in the PL. The
FCLK clocks are described in Chapter 25, Clocks.

 

 

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smarell
Community Manager
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Registered: ‎07-23-2012
The four fabric clocks (FCLK) are derived from individually selected PLLs in the PS. Hence, you can't assume them to be synchronous.

Do you have any specific requirement to use synchronous clocks (of different frequencies) in your design? If this is the case, why don't you use a single FCLK (say FCLK0) and drive to a MMCM/PLL on PL to derive synchronous clocks.
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lis_user1
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Registered: ‎11-17-2015

Thank you smarell and balkris. 

 

I need clocks of many frequencies, and it would be convenient if these four clocks are from the Customization wizard is synchronous. 

 

If they are not syn, then I will end up take other measures like MMCM. 

 

 

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smarell
Community Manager
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Registered: ‎07-23-2012
Since they are programmed individually, synchronization is not guaranteed. You can use MMCM/PLL in PL to generate synchronous clocks.
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balkris
Xilinx Employee
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Registered: ‎08-01-2008

Checked with timing team and it seems the four clocks that are generated by the PS are completely asynchronous to each other with no relationship to other PL clocks.
The four clocks are derived from individually selected PLLs in the PS. Each of the PL clocks are independent output signals that produce suitable clock waveforms for PL use.

Thanks and Regards
Balkrishan
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balkris
Xilinx Employee
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Registered: ‎08-01-2008
@lis_user1 i would like to know if you have any further questions on this issue
Thanks and Regards
Balkrishan
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lis_user1
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Registered: ‎11-17-2015

Not at the moment. Thank you. 

 

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