UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer swansonma
Observer
741 Views
Registered: ‎08-07-2018

Artix 7 De-Sequencing

Hello,

 

I am working with the Artix 7 (XC7A200T-1FBG484C) and am wondering how important de-sequencing is in terms of device reliability. I have the rails setup to de-sequence in the correct order but after observing the rails on an actual unit, the 1st rail that is supposed to come down (3.3V) does not have enough draw on it to fall below the other rails before they start to de-sequence. Is it imperative that this rail drop before the other rails? i.e. should I be adding extra load during de-sequencing or increasing the de-sequencing time? 

 

The rails are 1.0V (VCCINT, VCCBRAM), 1.8V (VCCAUX, VCCADC), 3.3V (VCCO). Sequence up is 1.0V >> 1.8V >> 3.3V. De-sequence is 3.3V >> 1.8V >> 1.0V

 

The snapshot shows the 3.3V rail (purple), the 1.8V rail (yellow), the 1.0V rail (green) and a sequencer fault line (red). 

 

Thanks,

Matt

scope_18.png
0 Kudos
5 Replies
Xilinx Employee
Xilinx Employee
689 Views
Registered: ‎06-02-2017

Re: Artix 7 De-Sequencing

Hi swansonma,

 

From DS181, if the power sequence is not satisfied, "the minimum current draw and ensure that the I/Os are 3-stated at power-on" cannot be guaranteed. 

The requirement is related to  device reliability is "The voltage difference between VCCO and VCCAUX must not exceed 2.625V for longer than TVCCO2VCCAUX for each power-on/off cycle"

-------------------------------------------------------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
--------------------------------------------------------------------------------------------------------------------------------------------
0 Kudos
Observer swansonma
Observer
673 Views
Registered: ‎08-07-2018

Re: Artix 7 De-Sequencing

Zhiq,

 

Thank you for the response. It makes sense that excess current could be drawn during shutdown. Fortunately, this shouldn't be an issue and may actually help bring a rail down faster. 

 

As for device reliability, I do meet the allowed time per power cycle for VCCO(3.3V) - VCCAUX(1.8V) > 2.625V (300ms @ 125C). Are there any other concerns in powering down in this way? 

 

Thanks,

Matt

0 Kudos
Xilinx Employee
Xilinx Employee
663 Views
Registered: ‎06-02-2017

Re: Artix 7 De-Sequencing

I don't think there is any other concerns except for these two listed on the datasheet.

-------------------------------------------------------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
--------------------------------------------------------------------------------------------------------------------------------------------
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
652 Views
Registered: ‎06-30-2010

Re: Artix 7 De-Sequencing

from a device point of view the only spec that can actually damage the device is the Tvvco2vccaux. If that is not violated then the implication are potential additional current draw during an incorrect sequence (due to the many possibilities we only characterize the data sheet sequence). The other issue is there could be a glitch so that could cause problems with device connected to the FPGA but is very application specific.
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Observer swansonma
Observer
614 Views
Registered: ‎08-07-2018

Re: Artix 7 De-Sequencing

jheslip, 

 

Thanks for the response. What do you mean by a glitch? Do you mean that the state of the outputs are not determined during the power-down, where they would be if the right de-sequence was followed?

 

Matt

0 Kudos