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Observer
Observer
4,736 Views
Registered: ‎08-14-2015

Artix-7 FPGA separation of essential bits

Hi to everyone,

 

I have some questions regarding the classifications of the essential bits in prioritized bits and critical bits. I know that the critical bits are known only by designer (I in my case), so I am interested in the prioritized bits.

I had instantiated the SEM IP Core (v4.1) on Artix-7 FPGA (ARTY-7 board) using Vivado. And I used the following command:

set_property BITSTREAM.SEU.ESSENTIALBITS YES [current_design]

Which generates me a text report with the following content:

“This design has 143810 essential bits out of 14663584 total (0.98%)”

And also and .ebc  file and .ebd file.

Now, from this forum, I find out that the .ebd file contains the mask (highlighted by ’ 1’ char) of “the essential bits” (which on counting are 143810 => see the previous report), and the .ebc file contains |the essential bits” highlighted by the .ebd file, either they are 0 or 1.

 

Some questions now:

 

  1. I suppose that total number of essential bits which are on the header either .ebc or .ebd file, 14663584 (in my case), is the total CRAM size. I am right on this lead?
  2. I suspect that the 143810 number, given in the log report are the prioritized bits. Because I started to inject errors outside those addresses of the 143810 bits, and the SEM IP report me that some addresses are essential, and other does nothing (is not injecting). Can someone confirm me this lead also?

I hope somebody can respond me, because I dont find any answer nowhere.

 

Thank you in advance,

Vlad

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Xilinx Employee
Xilinx Employee
4,703 Views
Registered: ‎09-05-2007

First of all the EBD and EBC files are consistent with the range of configuration memory in the device that is covered by the Readback CRC scanning mechanism and SEM IP. This included everything that would be expected to remain static during normal operation. Note that an initial configuration bit stream included many more bits that define the initial contents of all Block Memories. Since BRAM contents would be expected to change during operation they are not part of the Readback CRC scan. If you need to protect BRAM contents then look at using the optional ECC feature built in to very BRAM.

 

The standard EBD file (generated using the ‘set_property’ that you have stated) defines all the bits that are used to define your design. The EBD file tells you which bits are ‘non-essential’ and which bits are ‘essential’. The EBC file is the actual states of each configuration bit.

 

The bits marked ‘0’ in the EBD file are the non-essential bits and will be a mixture of configuration cells that do not describe your design and ‘holes’ in the memory map for which there are no physical cells in the device (in the region of 10%).

 

The bits marked ‘1’ in the EBD file are the essential bits. All of these bits have something to do with the definition of your design in the device. It is very tempting to think that if an SEU were to flip any of these bits then the design would stop working correctly. In practice, only a sub-set of these bits will impact the operation of the design when flipped and it is that sub-set that we call the ‘critical bits’. The critical bits are those that change the description a circuit that is actively being used and in a way that means that the logical values being generated by that circuit are incorrect at a time that they are being used later in the path. So for example, if a circuit is effected and generates different values which are applied to the D-input of a flip-flop then then those values will only have any impact if the flip-flop is both clocked and enabled. As such, it is very difficult to predict which bits are critical and error injection using the SEM IP is best way to evaluate the percentage of essential bits that fall into the critical category.

 

You can identify (tag) particular circuits in your design and have Vivado generate a ‘prioritised essential bits’ file. This is the same format as the standard EBD file but now the bits marked ‘1’ are only the essential bits associated with the definition of the tagged circuits rather than your whole design. As such, they are a sub-set of the total essential bits. It is important to appreciate that, just like the standard EBD file, only a sub-set of the essential bits will be critical bits.

 

Does this help?

Ken Chapman
Principal Engineer, Xilinx UK
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Observer
Observer
4,698 Views
Registered: ‎08-14-2015

Hi chapman,

 

Thank you for your answer, it helps in some way.

In your last phrase, about the ‘prioritised essential bits’ file, how can be generated in Vivado?

 

 

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Xilinx Employee
Xilinx Employee
4,629 Views
Registered: ‎09-05-2007

When I first saw your count of essential bits was so low (<1%) I thought you were already generating a ‘prioritised essential bits’ especially as you mentioned ‘prioritised’ in your opening sentence. It now appears that you have started with a very small design so therefore I strongly recommend (and I really mean; strongly recommend) that you now take the time to become fully acquainted with the standard EBD file and what essential bits really mean in practical terms before you progress to ‘prioritised essential bits’.

 

I have been using essential bit files for about 6 years and I can only recall two occasions in which I felt the need to be more selective with my EBD information and use ‘prioritised essential bits’. I would therefore suggest that you work with the standard EBD file for now. If you do then see need for ‘prioritised essential bits’ we can pick up on that again later in a new thread on this forum. I believe you now have enough information to answer the questions that you started this thread with and I just really want to be certain you understand what you have so far before adding more variables to the game.

Ken Chapman
Principal Engineer, Xilinx UK
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Observer
Observer
4,522 Views
Registered: ‎08-14-2015

Dear Ken,

 

Yes, you are right, I had instantiated only the SEM ip core.

Many thanks for your answers. I will make a higher design and also, I will get more familiar with the EBD file.

 

Best Regards,

Vlad

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Registered: ‎10-21-2019

Hi Ken,

In my development environment, I get below Essential Bits from the .ebd

This design has 9,196,587 essential bits out of 226104256 total (4.07%).

I am very interested to tag particular circuits in myt design and have Vivado generate a ‘prioritized essential bits’ file?  

Appreciate your help.

Mustafa

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