Hello expert's!
I have a custom board artix-7 XC7A100T-2FGG484 based. So i'm trying to simulate (in chip scope) first channel of GTP transceiver in loopback mode (LOOPBACK = "001") and here is a strange thing that i saw on the RXDATA output. Sometimes byte's swapping, sometimes they just wrong and comma detection didn't catch the real comma, they catching everything but comma...
first of all, i'm using:
ISE Design Suite 14.7 (same ChipScope version);
7 Series FPGAs Transceivers Wizard version 2.7;
I have a 180 MHz LVDS clock generator and 5.76 Gbps line rate of GTP. Clock connected in a wrong place (non MGTREF clocking place), but i have an external out of MGTREF0 clock and with external generator all work's the same baddly. I use a PLL1, DATA width 16 bit's, without encoding. Enable TX buffer, RX buffer (RXOUTCLK as a source of RXUSRCLK).
I use a comma with these setting's:
-
...
ALIGN_COMMA_DOUBLE => ("FALSE"), ALIGN_COMMA_ENABLE => ("0011111111"), ALIGN_COMMA_WORD => (2), ALIGN_MCOMMA_DET => ("TRUE"), ALIGN_MCOMMA_VALUE => ("1010000011"), ALIGN_PCOMMA_DET => ("TRUE"), ALIGN_PCOMMA_VALUE => ("0110101110"), SHOW_REALIGN_COMMA => ("TRUE"),
...
Enable:
- Decode valid comma only;
- two byte boundaries;
- enpcommaalign enable (and i'm trying use it as a chain with rxcommadet, but byte swapping the same)
RXBYTEISALIGNED is always high and RXBYTEREALIGN always low
For TXDATA i'm using little bit modifying pattern generator from the example design and catch data from rxdata right in chipscope without any change's. For pattern i'm using a counter (AEAE, 001, 002, ... , 007C, 007D, AEAE) when repeating all the same way again.
What i'm doing wrong?
GTP receiver need an external byte swapping module in cases when it occur?
Maybe need more delay's or something?
Any help please.
PS Sorry if it's a dumb question's
Thank's!
