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Visitor agianik0
Visitor
5,522 Views
Registered: ‎03-19-2015

Artix 7 - Hot plugging - Problem with output state of I/Os

On our Artix-7 board we follow for the FPGA the recommended power-on sequence (VCCINT, VCCBRAM, VCCAUX, and VCCO), but the problem is that the 3.3V for the rest ICs of the board is powered at the beginning, together with VCCINT. This creates a situation similar to hot-plugging, because after the VCCAUX is applied, the VCCO rail of all banks is reverse biased through the clamp diodes to a voltage of around 2.9V. I know this is not supported, but it is the only way to fulfill the power-on sequence requirements of all the ICs on the board.

 

This 2.9V voltage can also be seen on the I/Os, having as consequence an undesired reset of the co-processor (is at that moment during the power-on sequence and this reset leads to a situation where the rest ICs except the FPGA are not correctly initialised).

 

The question is: Is there anything I can do to avoid this HIGH state of the I/Os between powering VCCAUX and VCCO?

 

One idea I have is to switch-on both VCCAUX and VCCO together. Then the I/Os would go directly to 3-state. But is this allowed? To power the two supply rails at the same time?

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4 Replies
Scholar austin
Scholar
5,523 Views
Registered: ‎02-27-2008

Re: Artix 7 - Hot plugging - Problem with output state of I/Os

a,

 

Turning everything ON all at once is just fine.  The ONLY sequence not allowed would be in the data sheet, stated specifically as to avoid (and why). Note there are no sequences prohibited, other than the Vccaux vs. Vcco (which is irrelevant if simultaneous).

 

The recommended sequence is the one used in test, so 100% of the parts get tested to that sequence.  Power on currents specified only apply to that sequence.  Other sequences may have slightly different power in current requirements.  Powering ON Vcco through the protection diodes will not damage the device, but powering ON all at once will mean IO remain tri-state until DONE goes high (when the bitstream takes over).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Visitor agianik0
Visitor
5,486 Views
Registered: ‎03-19-2015

Re: Artix 7 - Hot plugging - Problem with output state of I/Os

UPDATE: Unfortunately this was not the solution. I tried powering the VCCO together with the VCCAUX or with the VCCINT, but what I get is that the IOs have a state of around 700-800mV after the VCCINT comes up. As soon as the VCCAUX starts coming up the IOs have a voltage of around 3.3V (my VCCO) or 2.8V and when VCCAUX is up they go to 3-state. The PUDC_B is connected HIGH.

 

Why is this happening?  Is it possible to eliminate this pulse? The pin I measured didn't have anything connected on it.

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Xilinx Employee
Xilinx Employee
5,363 Views
Registered: ‎08-01-2012

Re: Artix 7 - Hot plugging - Problem with output state of I/Os

If you do not follow data sheet recommended power-up sequence then IO state is un-predictable during Power-up.

 

Please note that PUDC-B state affects after power-up and during configuration. When PUDC_B is high, internal pull-up resistors are disabled on each SelectIO pin during configuration. Obviously the IO state is un-predictable during power-up

 

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Scholar austin
Scholar
5,355 Views
Registered: ‎02-27-2008

Re: Artix 7 - Hot plugging - Problem with output state of I/Os

a,

 

Make the measurement with two resistors:  one 1K to ground, and a 1K to Vcco.

 

ground ------1K--------IO pin -----1L------Vcco

scope gnd              probe

 

If the device is tristate all through power on, you will see Vcco/2 the entire time (probe will follow Vcco/2 exactly).

 

If this measurement is the same, with and without the IO pin connected to the resistors and scope, the the device is working perfectly, regardless of sequence.

 

Then, without the resistors, if this does not work for you there is nothing that sequencing will solve (it is likely you do not have a strong enough pullup or pulldown needed to make it work properly).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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