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Visitor bitfiddler
Visitor
8,023 Views
Registered: ‎10-04-2013

Artix-7 LVDS Clock Input HR Bank with VCCO=1.8V

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Hi, 

 

I have a clock coming from a 2.5V LVDS clock buffer (http://www.onsemi.com/pub_link/Collateral/MC100EP210S-D.PDF) that I would like to use within the FPGA. 

 

The clock is connected to CC pins in the HR bank on the Artix-7 with VCCO=1.8V. 

 

Since HR banks only support LVDS_25, which require the VCCO to be at 2.5V, I have added an external termination resistor. 

 

Questions:

Is it ok to directly connect the output of the clock buffer to the HR bank?

Do I need to add AC couple capacitors and DC bias resistors at the input of the FPGA?

 

Thanks

 

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Xilinx Employee
Xilinx Employee
10,896 Views
Registered: ‎01-03-2008

Re: Artix-7 LVDS Clock Input HR Bank with VCCO=1.8V

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 > Since HR banks only support LVDS_25, which require the VCCO to be at 2.5V

This is true output, but inputs can be any VCCO from 1.5 to 3.3V in HR banks, except for the following case...

 

> I have added an external termination resistor. 

Yes, the use of the internal DIFF_TERM feature requires that VCCO is 2.5V in the HR bank so you need to add the external resistor.

 

> Is it ok to directly connect the output of the clock buffer to the HR bank?

Yes, because the absolute voltage that the input pin will see will not exceed your VCCO of 1.8V.

 

> Do I need to add AC couple capacitors and DC bias resistors at the input of the FPGA?

No, just the differential termination resistor.

------Have you tried typing your question into Google? If not you should before posting.
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Visitor bitfiddler
Visitor
8,021 Views
Registered: ‎10-04-2013

Re: Artix-7 LVDS Clock Input HR Bank with VCCO=1.8V

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Explorer
Explorer
8,016 Views
Registered: ‎02-22-2010

Re: Artix-7 LVDS Clock Input HR Bank with VCCO=1.8V

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Please look in UG471at the table Vcco and Vref Requirements for Each Supported I/O Standard.

 

Note 1 answers your questions:

  • Differential INPUTS for LVDS_25 standard can be placed in banks with Vcco levels that are different from the required level for outputs.
  • In some cases it might be necessary to provide an external circuit to both AC-couple and DC-bias the pins.

Regards,

Eze

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Xilinx Employee
Xilinx Employee
10,897 Views
Registered: ‎01-03-2008

Re: Artix-7 LVDS Clock Input HR Bank with VCCO=1.8V

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 > Since HR banks only support LVDS_25, which require the VCCO to be at 2.5V

This is true output, but inputs can be any VCCO from 1.5 to 3.3V in HR banks, except for the following case...

 

> I have added an external termination resistor. 

Yes, the use of the internal DIFF_TERM feature requires that VCCO is 2.5V in the HR bank so you need to add the external resistor.

 

> Is it ok to directly connect the output of the clock buffer to the HR bank?

Yes, because the absolute voltage that the input pin will see will not exceed your VCCO of 1.8V.

 

> Do I need to add AC couple capacitors and DC bias resistors at the input of the FPGA?

No, just the differential termination resistor.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com

View solution in original post

Visitor bitfiddler
Visitor
8,007 Views
Registered: ‎10-04-2013

Re: Artix-7 LVDS Clock Input HR Bank with VCCO=1.8V

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Thank you very much.
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