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Visitor
6,312 Views
Registered: ‎08-30-2016

## [Artix-7] MINI_LVDS_25 output seems to be exceeding spec

We are using an Artix-7 FPGA (XC7A35T-L2CSG325E) to drive 5 LVDS signals for interfacing with a TFT LCD.  We are using the MINI_LVDS_25 standard for these LVDS outputs.  However, we are seeing around 800mV differential output voltage on these MINI_LVDS_25 outputs (see RXIN0 on the scope capture below) which seems wrong given that the "DC and AC Switching Characteristics" document states that the maximum differential output voltage should be 600mV.  This may be problematic for our LCD because an 800mV differential voltage is outside of their operating specification.

Any idea why our measured differential voltage here is outside the stated spec for the MINI_LVDS_25 IO standard?

1 Solution

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Moderator
9,879 Views
Registered: ‎07-23-2015

## Re: [Artix-7] MINI_LVDS_25 output seems to be exceeding spec

@marshall.bussen wrote:

gnarahar - The footnote for VOD on the Artix-7 datasheet says that "VOD is the output differential voltage (Q_P - Q_N)" so that doesn't seem to leave much room for interpretation to me.

Yes, this is what I meant in my earlier post i.e. Va-Vb is nothing but QP-QN which is 440mV which is within the spec

@marshall.bussen wrote:

Are you perhaps thinking of VID?

Should have rephrased my sentence better. Yes, it is VID if you consider logic 1/0 detection. Also I meant to say, our spec specify how much P will be higher N in VOD too. So for e,g VOD max is 600mV, it means P will be higher than N by 600mV Max in the Output signal.

@marshall.bussen wrote:

Unfortunately we only have one single-ended probe for our high-speed scope so I cannot do any MATH functions but we do have some differential probes that measured this differential voltage as close to 800mV (see page 1 of this conversation), which is why I brought up this question.

OK, then yes you wouldn't be able to do the Math function. Regarding Differential Probes, you will get double of QP-QN

To clarify it better, I ran a quick IBIS simulation using the MINI_LVDS_25 buffer driving into a 100 ohm termination. Check the waveform and they are pretty much inline with what you see . Q & Qbar are single ended probes. Hope this clarifies.

- Giri
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15 Replies
Scholar
6,309 Views
Registered: ‎02-27-2008

## Re: [Artix-7] MINI_LVDS_25 output seems to be exceeding spec

m,

Are the driven inputs terminated properly (100 ohms, differential)?

Typically, when exterminated, the peak to peak voltage is double what is expected.

Also check to be sure you have selected the proper IO standard (MINI_LVDS_25 and not some other LVDS option).

Austin Lesea
Principal Engineer
Xilinx San Jose
Visitor
6,295 Views
Registered: ‎08-30-2016

## Re: [Artix-7] MINI_LVDS_25 output seems to be exceeding spec

Hi Austin -

The inputs are terminated with far-end 100 ohm differential termination resistors as expected. The receiving IC is part of the manufacturer's LCD assembly. I will try and have them provide me with the datasheet for their LCD controller, because at the moment I cannot say with any certainty exactly what I/O standard the LCD receiving IC is using.

We have checked again and these pins are definitely set for MINI_LVDS_25 standard.
Scholar
6,290 Views
Registered: ‎02-27-2008

## Re: [Artix-7] MINI_LVDS_25 output seems to be exceeding spec

m,

I suspect you should be able to measure 100 ohms from + to - on an unconnected (powered) LCD interface.

I would check that your ohm meter uses a low enough voltage so as not to damage the LCD electronics, however.

Finally, I would measure the signal at a 100 ohm termination (no LCD).

Austin Lesea
Principal Engineer
Xilinx San Jose
Visitor
6,283 Views
Registered: ‎08-30-2016

## Re: [Artix-7] MINI_LVDS_25 output seems to be exceeding spec

Good thinking to test out the signal without the LCD in the system!  I connected a 100 ohm 1% resistor on the far end of the LVDS pair *without* the LCD present, but I am still seeing a larger than expected voltage swing (~400mV).  Keep in mind this is looking at a single side of the differential LVDS signal but I would expect that each side should be 1/2 of the total swing, correct?

Scholar
6,278 Views
Registered: ‎02-27-2008

## Re: [Artix-7] MINI_LVDS_25 output seems to be exceeding spec

OK,

I would set this up differentially (A-B, also check that your probes are calibrated).  I have seen all sorts of setup issues in the past.  Assuming that a single ended measurement is an accurate depiction of what is happening is not safe (especially here where there is a question).

You are measuring at the load, correct?

Austin Lesea
Principal Engineer
Xilinx San Jose
Visitor
6,269 Views
Registered: ‎08-30-2016

## Re: [Artix-7] MINI_LVDS_25 output seems to be exceeding spec

Unfortunately it is going to be very difficult for us to locate our high-speed differential probe in the location that is necessary for probing this signal in a differential manner given how our hardware is set up. I did measure across the other signal in the LVDS pair with a single-ended probe and confirmed that it had the same amplitude (~ 420 mV).

The measurements are being done on either side of the 100 ohm termination resistor on the far end of the signal pair. The ground reference for the scope probe is a nearby ground pad for a ceramic bypass cap. The ground lead is a little bit long (15-20mm).
Scholar
6,267 Views
Registered: ‎02-27-2008

## Re: [Artix-7] MINI_LVDS_25 output seems to be exceeding spec

m,

What is you use two single ended probes (Ch 1 & Ch2)?  Can you capture that and post it?  Doesn't the scope have an A-B?  It isn't the rise or fall times here we are concerned with (do not need a differential probe).  Are you calibrated?

Understand there is a LVDS standard to drive 2X available, so I am concerned that is what is selected.

Austin Lesea
Principal Engineer
Xilinx San Jose
Scholar
6,265 Views
Registered: ‎02-27-2008

## Re: [Artix-7] MINI_LVDS_25 output seems to be exceeding spec

Looks like the max voltage for MINI_LVDS is what you are getting.

Look at the data sheet.

I think you want RSDS instead (lower Vod).

Austin Lesea
Principal Engineer
Xilinx San Jose
Visitor
6,261 Views
Registered: ‎08-30-2016

## Re: [Artix-7] MINI_LVDS_25 output seems to be exceeding spec

According to the datasheet the VOD for MINI_LVDS_25 and RSDS_25 are the same though:

I am trying to reconfirm this voltage amplitude with a second oscilloscope but unfortunately our signal is currently at ~40MHz.  I used a 15GHZ scope for all of my captures so far but our "next best" scope is only 500MHz so the bandwidth limitation starts to become a bit of a problem.  We can always reduce the frequency of this signal as a work around but that will take a little time to rebuild the FPGA image.

Unfortunately we only have one single-ended scope probe for our high speed (15GHz) scope.  We have special differential probes as well but those extremely difficult to use in the current configuration  - they need to be soldered to the board and have the probe leads taped down, etc.

You referred before to "a LVDS standard to drive 2X available"; what is that standard and how do we confirm that we are not set for that?

Scholar
5,077 Views
Registered: ‎02-27-2008

## Re: [Artix-7] MINI_LVDS_25 output seems to be exceeding spec

m,

I was in error, series 7 has no such 2x drive feature for LVDS.

What is your Vcco voltage for this IO?  Have you tried RSDS?

Again, do not worry about scope bandwidth.  500 MHz should be sufficient to see the peak voltage here.

Austin Lesea
Principal Engineer
Xilinx San Jose
Moderator
5,059 Views
Registered: ‎07-23-2015

## Re: [Artix-7] MINI_LVDS_25 output seems to be exceeding spec

From the scopeshots, I believe the output in within the specs.

If I look at the Single Ended scopeshot, Va = 1.512V and Vb = 1.072 for the CLK_P. If CLK_N is the inverse of this signal (which it should be being the differential), VOD = Va - Vb = 440mV which is closer to the Typ VOD for MINI_LVDS_25 per spec.

The differential probe is showing the true differential swing and hence almost double of (Va-Vb).

Our specs i.e. VOD is more of how high P signal needs to be above the N signal to be detected as a logic 1.

For e.g. taking the case of MINI_LVDS_25, for a Logic 1 to be detected, the P signals needs to be anywhere between 300mV - 600mv higher than the N signal. Similarly for Logic 0, N signal needs to be anywhere between 300mV - 600mv higher than the P signal.

If you are using the single ended probes, use CH1 for CLK_P and CH2 for CLK_N and use the inbuilt oscillocope Math cuntion of CH1-CH2 which will give you Va-Vb.

@austin Correct me if I am wrong regarding our specs

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
-----------------------------------------------------------------------------------------------------------------------
Visitor
5,042 Views
Registered: ‎08-30-2016

## Re: [Artix-7] MINI_LVDS_25 output seems to be exceeding spec

Apologies for my absence, I was out of the office sick the past couple of days.

Austin - Our VCCO for this bank is 2.5V.  I just RSDS_25 but the voltage swing looks almost identical (~450mV single-ended).  This is with the LCD out of the system, so the FPGA with some differential 100 ohm traces going to a 100 ohm termination resistor (measuring at the resistor pads).

gnarahar - The footnote for VOD on the Artix-7 datasheet says that "VOD is the output differential voltage (Q_P - Q_N)" so that doesn't seem to leave much room for interpretation to me.  it is rated for a max of 0.6V on both MINI_LVDS_25 and RSDS_25.  Are you perhaps thinking of VID?  Because talking about how high the voltage difference between the P/N signals is for a 1 to be detected doesn't really make that much sense when the pair is being used as an output, to me.  Unfortunately we only have one single-ended probe for our high-speed scope so I cannot do any MATH functions but we do have some differential probes that measured this differential voltage as close to 800mV (see page 1 of this conversation), which is why I brought up this question.

Visitor
5,040 Views
Registered: ‎08-30-2016

## Re: [Artix-7] MINI_LVDS_25 output seems to be exceeding spec

I'm going to try using PPDS_25 now, just to see if there is any differential voltage change.
Moderator
9,880 Views
Registered: ‎07-23-2015

## Re: [Artix-7] MINI_LVDS_25 output seems to be exceeding spec

@marshall.bussen wrote:

gnarahar - The footnote for VOD on the Artix-7 datasheet says that "VOD is the output differential voltage (Q_P - Q_N)" so that doesn't seem to leave much room for interpretation to me.

Yes, this is what I meant in my earlier post i.e. Va-Vb is nothing but QP-QN which is 440mV which is within the spec

@marshall.bussen wrote:

Are you perhaps thinking of VID?

Should have rephrased my sentence better. Yes, it is VID if you consider logic 1/0 detection. Also I meant to say, our spec specify how much P will be higher N in VOD too. So for e,g VOD max is 600mV, it means P will be higher than N by 600mV Max in the Output signal.

@marshall.bussen wrote:

Unfortunately we only have one single-ended probe for our high-speed scope so I cannot do any MATH functions but we do have some differential probes that measured this differential voltage as close to 800mV (see page 1 of this conversation), which is why I brought up this question.

OK, then yes you wouldn't be able to do the Math function. Regarding Differential Probes, you will get double of QP-QN

To clarify it better, I ran a quick IBIS simulation using the MINI_LVDS_25 buffer driving into a 100 ohm termination. Check the waveform and they are pretty much inline with what you see . Q & Qbar are single ended probes. Hope this clarifies.

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
-----------------------------------------------------------------------------------------------------------------------
Visitor
5,000 Views
Registered: ‎08-30-2016