10-25-2018 02:28 AM
I'm using an Artix-7 to generate clock frequency sweeps between 36 KHz and ~600 MHz.
In detail, im using an MMCM with the CLKOUT4_CASCADE attribute set, and for dynamic reconfiguration I am using modified code from the application note XAPP888 (MMCM and PLL Dynamic Reconfiguration)
Only integer values for multiply, divide and the O4-O6 dividers are used while respecting the minimum and maximum frequencies of the VCO.
Functionality is confirmed in simulation (post-implementation), and the requested clock frequencies are also verified there.
However, moving to a real device, the MMCM clock output does not resemble a clock signal at all for certain frequencies. Frequencies where only multiply and divide are used (O4=O6=1) appear to be correct, i.e. 600 MHz is generated without issues.
Moving to lower frequencies by using O4 and O6 tends to disrupt the clock signal, which is displayed on the figures, as captured on a scope.
The question is, what could be the source of the problem? And what options are there for debugging this issue.
10-25-2018 05:01 PM
10-26-2018 05:09 AM
@bruce_karaffa No AC coupling is present
@jheslip The MMCM is running within the boundaries presented by the clocking guide, i.e. the VCO frequency is kept between 600 and 1400 MHz. The MMCM is locked, as verified by a debug core (ILA). I should mention, when M > 8 (and D=O4=O6=1) the MMCM fails to lock. This issue appears to be related to the lock registers, which are programmed with values from a look-up table provided by the XAPP888 application note. If I omit the lock registers during DRP, the MMCM locks just fine for M > 8 (and D=O4=O6=1) .
@lowearthorbit I don't have access to the scope for the moment, will provide asap.
Next steps I'll be undertaking consists of using ODDR output buffers, comparing static MMCM clocks (w/o DRP) and checking of the clock signals via LVDS.
10-28-2018 06:56 PM
How you are getting this signal out from FPGA?
I think this issue may be connected with the fact that clock signal is not coming correctly out from FPGA, wrong buffers on the clock line.
Can you show please the part of the code?
10-30-2018 01:34 AM
What is it like at the start before you do a DRP on it?
If I were you I would do the following, make a table of the details
Input signal/initial settings (M,D,O)/working out of the box with these settings (locked? Expected output?)/ DRP write (M,D,O)/Result?
This way it is clear what the behaviour is and what you write to it.