Artix-7 Microblaze second BRAM not showing in specified address. First 0x0 2nd added at 0x10_0000
I had the standard hello world with microblaze using 32K bytes BRAM. It worked. Also had cope using GPIO module worked.
In Vivado made a VGA driver and wanted a separate 32K bytes for screen memory. I wanted it accessible by microblaze at a non continuous address.. not following the first 32K. I choose 0x0010_0000.
So I added a port to the LMB - Local Memory Bus (which connect to DLMB) from microblaze. so LMB_S1_0 is first 32K bytes and new LMB_S1_1 is additional 32K bytes video memory. LMB_S1_1 (new port) connect to another LMB BRAM Controller. Its LMB Base Address (Auto) is at 100000 and high address (auto) is 107FFF and SLMB Address Decode Mask is 0x...0100000. All as it should be.
The 2nd port BRAM_PORTB for new upper 32K connects to VGA logic without going through LMB BRAM Controller (that's okay isn't it?). I just hold that port in read and change the address. Read 32-bits at a time into VGA module.
** PROBLEM IS when I read and write to that (0x10_0000) address from microblaze it really writes to the first 32K 0-7FFF. **
I see that in Vivado code I write to 0x0 and read from 0x10_0000. If I write more than a-little above 0x0010_0000 it trashes too much of the code memory at 0x0 so causes an exception.
I also used SDK debug memory editor and can write at 0x0010_0000 range and it updates 0x0 range.
These ranges should be set in the hardware so changing ranges in the SDK linker shouldn't affect it.
Address editor shows everything correct. Offset Adress 0x0010_0000 High Adress 0x0010_7FFF. I re synthesize from Vivado the Verilog and re export hardware (with bitstream) and relaunch SDK from vivado with any verilog or block diagram change.
I was using Vivado 2016.2 but updated to Vivado 2016.3 the latest and greatest.
Anybody know things I should check or common mistakes?