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4,033 Views
Registered: ‎08-30-2016

Artix-7 Power Supply Ramp Time requirements

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Hello,

 

Are the Power Supply Ramp Time requirements listed in Table 7 of the Artix-7 DC and AC Switching Characteristics datasheet hard requirements or are they merely to prevent excess current draw on boot?  Some of our Artix-7 power supplies are ramping quicker than the minimum requirement (12us - 166us) and I need to know if I should take steps to rectify this for the safety of the part or if these quicker ramp times are acceptable for general use.

 

Thanks!

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Scholar
Scholar
7,317 Views
Registered: ‎02-27-2008

m,

 

Ramp on times in the data sheet apply to the specified power on values.

 

Ramping faster does require more current, primarily just to charge the bypass capacitors.  For example, there is ~ 16 uF of capacitance in package on the core, so getting to 1v in 1 microsecond implies:  I=Cdv/dt, 16E-6 * 1E6 = 16 amperes.

 

Doesn't have anything to do with the FPGA silicon itself.  It is all just charging capacitors.  No reliability issues, as you are only 'stressing' your own power supply.

 

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

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Highlighted
Scholar
Scholar
7,318 Views
Registered: ‎02-27-2008

m,

 

Ramp on times in the data sheet apply to the specified power on values.

 

Ramping faster does require more current, primarily just to charge the bypass capacitors.  For example, there is ~ 16 uF of capacitance in package on the core, so getting to 1v in 1 microsecond implies:  I=Cdv/dt, 16E-6 * 1E6 = 16 amperes.

 

Doesn't have anything to do with the FPGA silicon itself.  It is all just charging capacitors.  No reliability issues, as you are only 'stressing' your own power supply.

 

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

View solution in original post