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jeyalakshmi
Visitor
Visitor
5,469 Views
Registered: ‎07-11-2012

Artix-7 Power up sequence

Hi,

I am using the Artix-7series device in my new design. As per the datasheet, I have concluded the below power-up sequence order.

              VCCINT/VCCBRAM(1V0)-->MGTAVCC(1V0)-->VCCAUX(1V8)-->VCCO(3V3&2V5)-->VTT(1V2)

 

In my design, I am using two different bank voltages like 3V3 and 2V5.

My question is can i power on the 2V5 & 1V2 output at same time after 3V3output is up?.

Please clarify.

 

Thanks,

Jeyalakshmi

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austin
Scholar
Scholar
5,466 Views
Registered: ‎02-27-2008

Yes,

 

Any sequence is allowed unless the data sheet states a particular sequence is NOT allowed.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
gszakacs
Instructor
Instructor
5,452 Views
Registered: ‎08-14-2007

While coming up in a certain order might not violate the data sheet or cause any device damage, there are system issues to consider.  For example if the first Vcco to come up is the one on the config bank (Bank 14 for most 7-series) then if the other Vcco is not up within the time it takes to configure, you will start up with a powered down bank.

 

Also it's not clear what VTT means.  Is that just the termination voltage for SSTL or did you mean the MGT VTT supply?  Typically termination supplies with a voltage set as a ratio of the supply voltage (typically 1/2 for Vtt using SSTL signalling) should come up with or after the supply they're referenced from.  These would not connect directly to the FPGA.

-- Gabor
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jeyalakshmi
Visitor
Visitor
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Registered: ‎07-11-2012

 

Hi,

FYI. VTT means MGTAVTT.

I am giving the 2.5V to Bank16 and other banks are powered up by 3.3V. Please let me know this may cause any damage on device.

 

 VCCINT/VCCBRAM(1V0)-->MGTAVCC(1V0)-->VCCAUX(1V8)--​>VCCO(3V3&2V5)-->MGTAVTT(1V2)

 

My question is can i power on the 2V5 & 1V2 output at same time after 3V3output is up?.

Please clarify.

 

Thanks,

Jeyalakshmi

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austin
Scholar
Scholar
5,384 Views
Registered: ‎02-27-2008

j,

 

I already answered that question.

Austin Lesea
Principal Engineer
Xilinx San Jose
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