10-08-2018 11:02 AM - edited 10-08-2018 11:09 AM
I'm working on a project where I'm migrating from a Spartan 3 to an Artix 7. In the Spartan 3 design we have the ability to reprogram the prom(holding the bitstream) after the device is loaded and running by driving the CCLK, CS, MISO, MOSI pins. When moving to the Artix 7 I found that the CCLK pin is now a dedicated pin and can't be driven directly by logic.
I've heard that it is possible to use the ICAPE2 module to do the programming of the prom but I can't seem to find out exactly how. I can't even seem to find a definition of the primitive.
So my questions are
1. Is it possible to have the ICAPE2 module do the programming of the flash? What I mean here is that I want to receive a bitstream remotely then I want to pass this off to the ICAPE2 module which will then handle the actual programming of the flash.
2. In xapp 1081 it references a file 'SpiFlashProgrammer.vhd' which it says programs the flash. I can't seem to find this file in any of the example projects. Does this file use the ICAPE2 primitive or is it a logic flash programmer? I ask because I was trying to find an example design using the ICAPE2 for reprogramming.
Thank you for any help!
Edit: I should mention that I've heard that the STARTUPE2 primitive that lets me control the CCLK with logic. I've just been instructed to see if we can have the ICAPE2 primitive do all the work of programming the flash.
10-08-2018 01:15 PM
10-08-2018 01:15 PM
10-08-2018 01:51 PM - edited 10-08-2018 01:58 PM
Thank you very much for the detailed response. I think those PDFs and projects clear up most of my confusion.
One more quick question for clarification. From what I read in the sources posted the ICAPE2 module is not capable of re-writing the flash, correct? I believe it can only read from the flash. So if I want to reprogram the FPGA with a new bitstream I should reprogram the flash with logic and then use the ICAPE2 primitive with the IPROG command to reprogram the FPGA from flash. Please let me know if anything there was incorrect.
Edit: added clarification about reprogramming the FPGA.
10-08-2018 02:01 PM