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Observer ikalogic
Observer
455 Views
Registered: ‎08-23-2011

Artix 7 and DDR deserializer: clearing some doubts

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Hi!

 

I am coming from Spartan / ISE world (please take this into consideration before judging my questions ^^ )

So, I am trying to understand what is the best strategy to deserialize 200MHz DDR (400 Mbps) 8 bits data coming into the FPGA from ADC (with the DDR clock also being provided by the ADC)

I have made some reading (UG471 and PG070), but given my past history (spartan 6) I need to be sure i am getting this right and not making any false assumption:

First, i am going to generate a SelectIO IP core to deal encapsulate the SERDES blocks

1- From my understanding, the IDELAYCTRL is only used to calibrate the tap delay, it that right?

2- Also, on its own, IDELAYCTRL cannot perform any kind of data path delay calibration to put the clock and right spot, right?

3- In Artix 7, there is no equivalent to the automatic calibration similar to what is described in XAPP1064 for Spartan 6, right? Or maybe the calibration done in XAPP1064 actually only compensates for the lack of IDELAYCTRL ?

4- Which leads me to conclude that, in Artix-7, I'm free to figure out what calibration algorithm to use to iterate through the data path delay taps until it find the best delay that places the clock at the center of the data eye. (which is cool, i just don't want to reinvent the wheel)

If i am correct about the above, then finally, i intend to use a "training pattern" that can optionally be generated by the ADC i am using, which leads me to the final question: 

5- What if the ADC i am using (or whatever other source is that) do not offer any training mode, is there a way to generate a "fake" reference signal at the input PADs (ignoring external signals during that time), exactly as it's done in spartan 6's XAPP1064 calibration?

Thanks a lot for shedding some light on those questions or pointing me to the right direction!

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1 Solution

Accepted Solutions
Historian
Historian
417 Views
Registered: ‎01-23-2009

Re: Artix 7 and DDR deserializer: clearing some doubts

Jump to solution

1- From my understanding, the IDELAYCTRL is only used to calibrate the tap delay, it that right?

Yes.

2- Also, on its own, IDELAYCTRL cannot perform any kind of data path delay calibration to put the clock and right spot, right?

Correct.

3- In Artix 7, there is no equivalent to the automatic calibration similar to what is described in XAPP1064 for Spartan 6, right? Or maybe the calibration done in XAPP1064 actually only compensates for the lack of IDELAYCTRL ?

Also correct - there is no equivalent to the automatic calibration of the Spartan-6. The reason for the difference is that the IDELAY in the Spartan-6 is nothing like the IDELAY in the 7 series - not only is it not calibrated, but it operates on an entirely different mechanism; the Spartan-6 mechanism is far less flexible, but also consumes less die area and less power. However, due to its "unique" architecture, the "center aligned" automatic calibration came almost for free. Since the 7 series IDELAY is different, it does not.

4- Which leads me to conclude that, in Artix-7, I'm free to figure out what calibration algorithm to use to iterate through the data path delay taps until it find the best delay that places the clock at the center of the data eye. (which is cool, i just don't want to reinvent the wheel)

Yes. However, there are some APP notes like XAPP524 that give some ideas for solutions.

If i am correct about the above, then finally, i intend to use a "training pattern" that can optionally be generated by the ADC i am using, which leads me to the final question: 

5- What if the ADC i am using (or whatever other source is that) do not offer any training mode, is there a way to generate a "fake" reference signal at the input PADs (ignoring external signals during that time), exactly as it's done in spartan 6's XAPP1064 calibration?

Like XAPP524 shows, it is possible to do live dynamic calibration using only the clock - a fixed data pattern is not required. This can even be done "full time" while real data is being carried and without corrupting the data. This allows for the calibration mechanism to track the characteristics of the FPGA even as it varies over time (i.e. as the temperature of the FPGA changes).

Avrum

4 Replies
Historian
Historian
438 Views
Registered: ‎01-23-2009

Re: Artix 7 and DDR deserializer: clearing some doubts

Jump to solution

Before you dive into dynamic calibration, you should ask yourself whether the interface can be captured statically. At 400Mbps (2.5ns per data window), the answer can be "yes" depending on the timing of the ADC and the clocking architecture used.

Take a look at this post on constructing input interfaces.

Avrum

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Observer ikalogic
Observer
425 Views
Registered: ‎08-23-2011

Re: Artix 7 and DDR deserializer: clearing some doubts

Jump to solution

Thank you very much, very instructive post that i'll have to spend some quality time analyzing.

At some point, i'll still need to find some answers/confirmations to my questions. hopefully, i'll find them. Looking at the post you shared, i read between the lines that Spartan 6 has things that Artix 7 do not have, which would make a little bit more sense in my mind! (I was assuming artix 7 would have all the features of the spartan 6 or better equivalents, but i think this has misled me)

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Historian
Historian
418 Views
Registered: ‎01-23-2009

Re: Artix 7 and DDR deserializer: clearing some doubts

Jump to solution

1- From my understanding, the IDELAYCTRL is only used to calibrate the tap delay, it that right?

Yes.

2- Also, on its own, IDELAYCTRL cannot perform any kind of data path delay calibration to put the clock and right spot, right?

Correct.

3- In Artix 7, there is no equivalent to the automatic calibration similar to what is described in XAPP1064 for Spartan 6, right? Or maybe the calibration done in XAPP1064 actually only compensates for the lack of IDELAYCTRL ?

Also correct - there is no equivalent to the automatic calibration of the Spartan-6. The reason for the difference is that the IDELAY in the Spartan-6 is nothing like the IDELAY in the 7 series - not only is it not calibrated, but it operates on an entirely different mechanism; the Spartan-6 mechanism is far less flexible, but also consumes less die area and less power. However, due to its "unique" architecture, the "center aligned" automatic calibration came almost for free. Since the 7 series IDELAY is different, it does not.

4- Which leads me to conclude that, in Artix-7, I'm free to figure out what calibration algorithm to use to iterate through the data path delay taps until it find the best delay that places the clock at the center of the data eye. (which is cool, i just don't want to reinvent the wheel)

Yes. However, there are some APP notes like XAPP524 that give some ideas for solutions.

If i am correct about the above, then finally, i intend to use a "training pattern" that can optionally be generated by the ADC i am using, which leads me to the final question: 

5- What if the ADC i am using (or whatever other source is that) do not offer any training mode, is there a way to generate a "fake" reference signal at the input PADs (ignoring external signals during that time), exactly as it's done in spartan 6's XAPP1064 calibration?

Like XAPP524 shows, it is possible to do live dynamic calibration using only the clock - a fixed data pattern is not required. This can even be done "full time" while real data is being carried and without corrupting the data. This allows for the calibration mechanism to track the characteristics of the FPGA even as it varies over time (i.e. as the temperature of the FPGA changes).

Avrum

Observer ikalogic
Observer
411 Views
Registered: ‎08-23-2011

Re: Artix 7 and DDR deserializer: clearing some doubts

Jump to solution

Thanks a lot!

 

That clears up many things!

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