Artix-7 configuration - unequal bank voltages

[16r8]

Hello, I want to do this:

- Artix 7A100.

- Slave serial configuration.

- VCCO_0 is 1.8V, and my CCLK is 1.8V.

- VCCO_14 is 2.5V, and my DIN voltage is to be determined.

Will that work?

Does my DIN need to be 1.8V or 2.5V?

Should I set CFGBVS low or high?

UG470 should simply say what CFGBVS does inside the FPGA, rather than giving pages of confusing rules.

UG470 mentions "damage". Is it simply saying don't apply input voltage higher than VCCO, or does the FPGA have an unexpected self-destruct mechanism?

Thanks.

[tenzinc]

16r8,

Well DIN pins are on bank 14 so if your VCCO_14 is 2.5V then they should be the same. Also not sure if you've seen table 2-9 in UG470. Bank 0 and 14 should be the same voltage. UG470 does tell you what it does inside the FPGA. It a circuit select pin that determines whether the FPGA should use an lower voltage configuration circuit or a higher voltage one. Why do you want to set VCCO_14 to 2.5V? Damage is only a real concern when the input voltage to the FPGA is higher than then input FPGA bank voltage. The bigger concern here is reliability of having multi voltage lines for the same serial interface. The FPGA input thresholds are different at different VCCO voltages as LVCMOS is the IOSTANDARD used for configuration by default. 

Regards,

Tezz

[16r8]

Thank you for the quick response, and for clarifying the damage issue.

That answers the second question in my group of three questions - I will apply DIN at 2.5V level.

Please answer the other two questions

UG470 should provide a table or equivalent circuit diagram that explains how CFGBVS affects each pin's input threshold voltage, output drive voltage, etc.

[16r8]

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[borisq]

hi @16r8

please follow UG470 Table 2-6 for the connections of Vcco_0, Vcco_14, and CFGBVS.

Please see the snapshot below.

If it is violated, we cannot guarantee it can work.

Thanks,

Boris

[16r8]

Hi Boris,

Vivado DRC accepts my combination of Artix-7, Slave Serial, CFGBVS=GND, VCCO_0=1.8V, and VCCO_14=2.5V (14 is my LVDS I/O bank). DRC simply warns me to apply compatible configuration voltage. I think that means I can apply CCLK at 1.8V and DIN at 2.5V, but the message is unclear:

"WARNING: [DRC CFGBVS-7] CONFIG_VOLTAGE with Config Bank VCCO: The CONFIG_MODE property of current_design specifies a configuration mode (S_SERIAL) that uses pins in bank 14. I/O standards used in this bank have a voltage requirement of 2.50. However, the CONFIG_VOLTAGE for current_design is set to 1.8. Ensure that your configuration voltage is compatible with the I/O standards in banks used by your configuration mode. Refer to device configuration user guide for more information. Pins used by config mode: K18 (IO_L1N_T0_D01_DIN_14), L15 (IO_L3P_T0_DQS_PUDC_B_14), and T16 (IO_L15N_T2_DQS_DOUT_CSO_B_14)"

Vivado DRC and UG470 disagree. Which is correct?

I don't need a project solution - we avoided the situation another way.

However this DRC-vs-UG470 contradiction is bugging me. Can you please dig a little deeper than UG470?

Thank you