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Visitor haunma
Visitor
10,442 Views
Registered: ‎03-21-2011

Artix-7 decoupling: >> 1 capacitor per power pin?

I know, yet another post with a question about decoupling.  I *have* read the others, and I think I understand the difference between Xilinx's conservative recommended size/number of capacitors, vs looking at one's own application, and finding a more customized answer.

 

That being said, I am baffled by the recommendations for high-frequency 0.47-uF caps in the Artix-7 PCB guide UG483 (v1.4).  It recommends 17 of them for Vccint on the FTG256 package.  There are only seven Vccint pins on the entire package.  Does it ever make sense to have more than one tiny capacitor per pin?  I can't imagine why, although I will readily concede my inexperience.  Could someone please enlighten me?  Thanks.

 

 

 

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11 Replies
Scholar austin
Scholar
10,441 Views
Registered: ‎02-27-2008

Re: Artix-7 decoupling: >> 1 capacitor per power pin?

h,

 

It is all about the inductance to the bypass capacitors.  If one can layout a power plane with lower inductance to get to the capacitors, then you win (including the inductance of the capacitors, themselves).


So, I would look at the gerber files for the Artix demo pcbs.

 

Do they use what we recommend? (Sometimes our demo pcb's didn't follow the recommendations in the past...)

 

How did they lay it out?

 

Given the Artix parts are wire bond, there isn't much you can do about inductance:  there is a WIRE to ground, and WIRE to Vccint...

 

But, I am now in Xilinx Research Labs (I don't have my 'ear to the rail anymore'), so maybe I am all wrong, and someone will post here how we are so clever, and acheived such and such an improvement, over previous solutions.  Its  possible (I'm wrong, here!?).

 

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Visitor haunma
Visitor
10,421 Views
Registered: ‎03-21-2011

Re: Artix-7 decoupling: >> 1 capacitor per power pin?

Thanks Austin,

 

Your points are well taken.  I will have a look at open Artix designs (are they any yet?) and see what they used.  But the crux of my question, I think, was how you could have more than one capacitor, of a given size, per ball.  Would that ever make sense, for anyone, in any place, at any time, for any application?  I guess I'm just not understanding how trying to cram three 0.47 uF caps *per Vccint ball* would result in significantly lower inductance than one per ball.  Surely this is a case of diminishing returns because, as you said, there's still that wire.

 

I was sort of hoping someone would take a look at that document and confirm my suspicion, that it's actually a mistake :)

 

 

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Highlighted
Visitor haunma
Visitor
10,285 Views
Registered: ‎03-21-2011

Re: Artix-7 decoupling: >> 1 capacitor per power pin?

So I noticed today that Digikey has availability on one of the Artix-7 parts.  I still haven't seen much in the way of eval or development boards for Artix, however.  Does anyone know of an open design with schematic and gerbers that one could refer to as a reference?

 

I'm also still hoping for a definitive answer to my original question:  Is the layout guide (UG483) in error, or are they really recommending multiple capacitors, of the same type and value, per ball?

 

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Scholar austin
Scholar
10,281 Views
Registered: ‎02-27-2008

Re: Artix-7 decoupling: >> 1 capacitor per power pin?

h,

 

Depending on the number of layers, and the layout, yes three capacitors can be lower inductance/more capacitance than one.

 

The pcb user's guide shows how to,and not to, layout the capacitors.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Newbie xiaodiansai
Newbie
8,637 Views
Registered: ‎08-19-2014

Re: Artix-7 decoupling: >> 1 capacitor per power pin?

hello,

I got the schematic of XUP Nexys4 Board, as a reference to design the Artix-7 FPGA.

But when I compare the PCB Decoupling Capacitors of  Nexys4 Board with the user guide UG483, the difference confused me.

I'm a green hand. Can I just follow the design of Nexys4 Board?

The FPGA I used is XC7A200t_FBG484, for Data collection and calculation.

 

Thanks a lot.

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Scholar trenz-al
Scholar
8,627 Views
Registered: ‎11-09-2013

Re: Artix-7 decoupling: >> 1 capacitor per power pin?

Hi

 

its complicated and confusing sometimes, the rules and boards that do not follow rules and still work. or maybe work.

 

seeing a board PCB that is KNOWN to work can not be taken as good example for if we do the same it must also work.

 

a lot of 0201 can be placed below FPGA on HDi boards, but you must always use some brain to decide where the small caps make sense

 

about GERBERS from vendor X.Y.Z - I was amazed looking at VC709 gerbers - the board has 40A VCCINT supply, and for this 40A rail maximum current path is in one place about only 1.8 mm wide on single layer, sure some current takes other paths as well, but for me it looked brr.....

 

1.8m wide 0.35um 40A ? scary?

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Newbie xiaodiansai
Newbie
8,622 Views
Registered: ‎08-19-2014

Re: Artix-7 decoupling: >> 1 capacitor per power pin?

How a newbie quick start for design?
Can you give me some suggestions?
Thanks.
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Adventurer
Adventurer
8,595 Views
Registered: ‎02-16-2014

Re: Artix-7 decoupling: >> 1 capacitor per power pin?

学习借鉴!
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Xilinx Employee
Xilinx Employee
8,584 Views
Registered: ‎01-03-2008

Re: Artix-7 decoupling: >> 1 capacitor per power pin?

> 1.8m wide 0.35um 40A ? scary?

 

I don't know where you saw this, but the VC709 VCCINT_FPGA 40A supply has two dedicated planes on layers 8 and layers 11.  There is no issue with delivering the 40A to the FPGA.  Possibly you have been confused by the voltage sense paths.

 

Power supply delivery and accuracy are a primary concern and the boards are simulated to ensure that there IR drop is kept to a minumum and the voltage sensing is placed in the correct locations for accuracy.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Xilinx Employee
Xilinx Employee
2,202 Views
Registered: ‎01-03-2008

Re: Artix-7 decoupling: >> 1 capacitor per power pin?

> Can I just follow the design of Nexys4 Board?

 

You should follow the PCB recommendations in the official Xilinx documentation which in this case is UG483.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Adventurer
Adventurer
736 Views
Registered: ‎03-29-2008

Re: Artix-7 decoupling: >> 1 capacitor per power pin?

I still do not see a conclusive statement from Xilinx on using multiple capacitors for a single power pin.  UG483 seems to say you should but it sounds like gross overkill.

 

Artix and Spartan are low cost families.

 

Can Xilinx please give an definitive answer?

 

Thank You

Nick

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