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Voyager
Voyager
2,645 Views
Registered: ‎05-25-2016

Artix 7 - done pin stuck low - no JTAG comm

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Hello,

 

I'm trying to get a custom board design to boot correctly.  I'm using the XC7A35Tcpg236 part.  I'm powering the device with 1.0,1.8 and 3.3 which all come up and look ok.  They come up with a soft start time of 5-10mS in the order of 1.0-1.8-3.3.  This seems  to match the datasheet recommendations.  I can't communicate with the part via JTAG though and I'm unsure why.  The message I get from Vivado 2017.2 says to check JTAG connection and verify the board  is powered  which I have.  

 

I noticed that the  INIT_B pin goes high shortly after power up but the DONE pin never  does.  I have  a spansion flash part connected, but nothing has been programmed into the flash or the FPGA.  I'm using the Platform Cable USB  II (DLC10) and am plugging in the flying leads for tck,tdi,tdo and tms into my board.  Do I need any other signals?  Does anyone have any suggestions as to why there would  be no jtag connection or why the done signal is stuck low?  A lot of the debugging techniques I'm finding are based around having a JTAG connection.  

 

Schematic configuration:

1.jpg

 

1.jpg

 

 

1.jpg

 

 

 

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Moderator
Moderator
3,637 Views
Registered: ‎07-23-2015

@m3atwad You have Mode pins for Master SPI settings and with no data in SPI flash, there is no configuration that can happen. So DONE pin is low. However JTAG can override MODE pin settings and be used to program the FPGA.  

 

You need to connect VREF as well along with TCK, TMS, TDI, TDO. Your status LED on the Platform cable must turn GREEN. Check this https://www.xilinx.com/support/documentation/data_sheets/ds593.pdf for more details on VREF connection and status LED color status. 

- Giri
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Voyager
Voyager
2,644 Views
Registered: ‎05-25-2016

Here is a more clear screenshot of  bank 14

 

4.jpg
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Moderator
Moderator
3,638 Views
Registered: ‎07-23-2015

@m3atwad You have Mode pins for Master SPI settings and with no data in SPI flash, there is no configuration that can happen. So DONE pin is low. However JTAG can override MODE pin settings and be used to program the FPGA.  

 

You need to connect VREF as well along with TCK, TMS, TDI, TDO. Your status LED on the Platform cable must turn GREEN. Check this https://www.xilinx.com/support/documentation/data_sheets/ds593.pdf for more details on VREF connection and status LED color status. 

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
-----------------------------------------------------------------------------------------------------------------------

View solution in original post

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Voyager
Voyager
2,594 Views
Registered: ‎05-25-2016
Thank you for the reply! I will fix Vref today and see what happens.
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Voyager
Voyager
2,566 Views
Registered: ‎05-25-2016
Connecting Vref on the JTAG USB II programming pod to BANK0 Vcco (was 3.3V for me) fixed my issue. Thank you very much for the help gnarahar!
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