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Srikanth_Kacchu
Visitor
Visitor
386 Views
Registered: ‎07-01-2021

Artix 7 internal termination

Hi Xilinx,

I am having a FPGA (Artix-7) to level translator ( 74FCT164245). I checked the signal quality with and without series termination. With series termination signal quality is pretty good. But i can't provide the resistor on my board.

So is there any option to use internal termination in Artix 7 series. It will not have calibrated termination as it have only HR banks but what about uncalibrated termination? is there any options like that?

I am attaching my simulation results for your reference.

 

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drjohnsmith
Teacher
Teacher
341 Views
Registered: ‎07-09-2009

Many things to look at here,

why such a low line impedance, 50 ohms for such a slow signal ?

    

you have a 300 mm line, but no space for a series resistor ?

 

do you need such a fast edge speed, or drive strength, its only 35 MHz ?

   

could you look at a AC termination to ground at the receiver ?

 

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gszakacs
Instructor
Instructor
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Registered: ‎08-14-2007

I've found that the output impedance when using LVCMOS with 4mA output drive is close enough to 50 Ohms to reduce ringing to an acceptable level.  I suggest you try this (setting the output drive current to 4mA instead of the default 12 mA) on your test board with the zero Ohm resistor installed.  Note that the drive level is only a part of the output impedance equation.  Vcco also affects impedance somewhat.

-- Gabor
Srikanth_Kacchu
Visitor
Visitor
204 Views
Registered: ‎07-01-2021

This line is a bi-directional data, so I am trying to avoid termination here. We are having some 16 bits data-lines, so if I provide termination to all then it will be quite complicated. If the FPGA have internal termination then at least I can avoid this externally. So is it possible in Artrix-7 with package 1FBG676C?

As for now I am seeing around 200mV over/under shoot with 8 mA drive strength, which is best till now.

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Srikanth_Kacchu
Visitor
Visitor
202 Views
Registered: ‎07-01-2021

I tried with 4mA but it is giving non-monotonicity in signal. 8mA is working fine with some 200 mV over/under shoot. If I place 22/33 ohms series termination then it is getting reduced. But I wanna avoid these termination because these lines are 16-bits VME bi-directional data lines. Whether these termination will impact the signal when my FPGA is gonna receive the data?

That's why I wanna know whether this artix-7 with package 1FBG676C have any options for internal terminations or not?

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drjohnsmith
Teacher
Teacher
180 Views
Registered: ‎07-09-2009

Look in the data sheet for your part 

its a 7 series so , page 19 to 32

https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

in general, the 7 series has DCI / termination options, dependent upon the pin type you have used and if you have / need bias ,

https://www.xilinx.com/support/answers/45953.html

 

 

BUT 

 

a few things,

  for the future, sorting thsi sort of thing out retrospectivly is very very difficult

  Are you measuring this over ' under shoot with scope probe, are you using the long earth on the side of the probe, or the short earth on the actual tip

     if the former, the over under shoot might not even be there, 

 

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