02-13-2020 12:46 AM
what guidelines should be followed to get optimal pin placement? I need some help in following topics:
FPGA bank selection:
My chosen Artix7 device only have HR banks and same pin count in every bank, so as I understand there is no difference what FPGA bank I will chose?
Clock input placement:
MRCC or SRCC pins? In general MRCC would be better choice for this purpose?
Clock output pin placement:
I think there is no special pins for clock output, so any general purpose pin can be used?
How do I chose pins in FPGA bank for I/O to get optimal timing or SSN? I have source synchronous input interface and source synchronous output interface. Should i place interface pins next to each other? Is there any restrictions where pins with differenctial standarts can be placed, besides folowing P/N pairs?
02-13-2020 07:54 AM
02-13-2020 01:33 AM
02-13-2020 02:09 AM
Hi @vytbuit :
Adding to @drjohnsmith comments, if you are using MMCM, PLL,BUFG, BUFH etc. ie global clocking resources, then the MRCC and SRCC both can be used except the BUFMR (multi clock region buffer) which can be driven by MRCC only.
Refer https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf , page 24 for detailed information.
If you don't need BUFMR, then I believe its better to use the SRCC pins first.
02-13-2020 02:17 AM
Thank you @drjohnsmith for your answer. Can I kindly ask you to be more specific with your answers, because I know some basic principles but I dont have much real design experience with Xilinx FPGA and Xilinx tools.
Optimal timing you ask, let the tools do that for you,
How do I do that? Compile design without pins assigned and see what pin location tool suggests?
Clock out ? What clock out do you want to do ?
If its for a ADC / DAC , at any sort of frequency , dont do it .
Yes, for DAC. Can you explain why and then how should I do it? Use system synchronous design approach instead of source synchronous? I know that clock from FPGA resources have larger jitter which can cause some performace degradation for DAC compared to external clock generating IC but I dont have much real design experience to compare these two solutions.
the more stuff you have changing at once, on any one bank the more noise it will make, The more current they output drive, the more noise, The faster the slew rate, the more noise.
How do I check them?
Bottom line, if your un certain, do a test fpga design, see what the reports are BEFORE you lay your board out.
Yes, I am allready doing test design but I would like to know what I am doing and what Vivado are saying to me.
thank you @drjohnsmith
02-13-2020 07:54 AM