There are some older design advisories and presentations from Xilinx
stating that Artix-7 in speed grades: -2, -3 and wire-bond packages
(like CSG325) allows a maximum GTP data rate of 5.40 Gbps and only
flip-chip packages allow the full GTP data rate of 6.60 Gbps. Newer
documents from Xilinx either make no distinction between Artix
packages - setting the data rate limit at 6.60 Gbps for all devices or
(e.g. AR# 58162) recommend to leave certain banks unused or prohibits
certain neighbor I/Os to be used in order to reach GTP line rates over
6.00 Gbps in wire-bond packages.
We're planning to built a 2 x 6.25 Gbps receiver based on two GTPs in
the XC7A35T-2CSG325C. Is it generally possible? Is there any fresh
document from Xilinx defining data rate limits for 7 Series FPGAs,
which may be used as a reliable reference?
