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Anonymous
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Artix-7 wire-bond package GTP line rate limit. Is 6.25 Gbps possible in speed grade 2?

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There are some older design advisories and presentations from Xilinx
stating that Artix-7 in speed grades: -2, -3 and wire-bond packages
(like CSG325) allows a maximum GTP data rate of 5.40 Gbps and only
flip-chip packages allow the full GTP data rate of 6.60 Gbps. Newer
documents from Xilinx either make no distinction between Artix
packages - setting the data rate limit at 6.60 Gbps for all devices or
(e.g. AR# 58162) recommend to leave certain banks unused or prohibits
certain neighbor I/Os to be used in order to reach GTP line rates over
6.00 Gbps in wire-bond packages.

 

We're planning to built a 2 x 6.25 Gbps receiver based on two GTPs in
the XC7A35T-2CSG325C. Is it generally possible? Is there any fresh
document from Xilinx defining data rate limits for 7 Series FPGAs,
which may be used as a reliable reference?

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Xilinx Employee
Xilinx Employee
16,083 Views
Registered: ‎02-16-2014

Re: Artix-7 wire-bond package GTP line rate limit. Is 6.25 Gbps possible in speed grade 2?

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Xilinx Employee
Xilinx Employee
16,084 Views
Registered: ‎02-16-2014

Re: Artix-7 wire-bond package GTP line rate limit. Is 6.25 Gbps possible in speed grade 2?

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Anonymous
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Re: Artix-7 wire-bond package GTP line rate limit. Is 6.25 Gbps possible in speed grade 2?

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Great. thank you for a precise answer.
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Xilinx Employee
Xilinx Employee
8,309 Views
Registered: ‎02-16-2014

Re: Artix-7 wire-bond package GTP line rate limit. Is 6.25 Gbps possible in speed grade 2?

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hi @Anonymous

 

Glad that it helped.

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