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294 Views
Registered: ‎01-30-2018

Artix7: BUFIO to BUFR connection won't route when IDELAY added

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Hello,

I'm trying to clock parallel DDR data from a few IOs into ISERDES blocks, effectively bringing four samples at a time onto an SDR clock domain that's half the DDR clock frequency. This is source synchronous with an LVDS clock coming from the external device.

If I insert an IDELAY in the path, then the chain should look like:

LVDS clock in -> IBUFDS -> IDELAY -> BUFIO -> BUFR -> my clock region.

The BUFIO output is going both to the clock input of my ISERDES blocks, and the input of the BUFR whose output goes to the clkdiv input of the SERDES as well as whatever logic and memory blocks are receiving the output of the SERDES.

 

But, in this case the place and route tool for some reason will not route the output of the BUFIO to the input of the BUFR, even though they are right next to each other.

If I don't have any IDELAYs the tool routes everything. The design almost works but with a ramp function test pattern certain bit transitions cause the data word to not be captured properly and result in a spurious data point. So I figured I would need to tune the timing a little bit.

The tool doesn't seem to be telling me why it can't or won't route this clock into the BUFR's input. When I open up the floorplan and highlight the net it acknowledges that there should be a connection there, but doing a mouseover on the BUFR input shows status "not routed."

Any ideas on where else I can be looking for clues on this?

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262 Views
Registered: ‎01-22-2015

Re: Artix7: BUFIO to BUFR connection won't route when IDELAY added

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@sbattazzo_arc 

You got it !

Table 1-1 in UG472 is your go-to reference for clock connectivity in the 7-Series FPGAs.  Table 1-1 shows that BUFIO can only drive ILOGIC and OLOGIC in the same clocking region as the BUFIO (and cannot drive a BUFR).  The ISERDES is part of ILOGIC. 

As you found, ISERDES clocking for your application should follow Figure 3.6 in UG471.
ISERDESE2_clocking.jpg

Mark

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279 Views
Registered: ‎01-30-2018

Re: Artix7: BUFIO to BUFR connection won't route when IDELAY added

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OK, I think I may see what I did wrong.

The diagram I saw showing the output of the BUFIO going to the BUFR was from UG070 which is for Virtex-4. In the Artix-7 user guide the clock input goes to both the input of BUFIO and the input of BUFR in parallel.. will give that a try!

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263 Views
Registered: ‎01-22-2015

Re: Artix7: BUFIO to BUFR connection won't route when IDELAY added

Jump to solution

@sbattazzo_arc 

You got it !

Table 1-1 in UG472 is your go-to reference for clock connectivity in the 7-Series FPGAs.  Table 1-1 shows that BUFIO can only drive ILOGIC and OLOGIC in the same clocking region as the BUFIO (and cannot drive a BUFR).  The ISERDES is part of ILOGIC. 

As you found, ISERDES clocking for your application should follow Figure 3.6 in UG471.
ISERDESE2_clocking.jpg

Mark

View solution in original post

194 Views
Registered: ‎01-30-2018

Re: Artix7: BUFIO to BUFR connection won't route when IDELAY added

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Thank you!

Place and route did complete when I made this little change. Unfortunately messing with IDELAYE2 didn't seem to have much effect on my interface timing problem but that's now a separate topic, hopefully I can be self-sufficient but we shall see.

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