Artix7 ERROR: [Place 30-574] Sub-optimal placement

[lacosteaef]

Hello,

I'm getting the following message:

[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
	< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets fsync_IBUF] >

	fsync_IBUF_inst (IBUF.O) is locked to IOB_X1Y99
	 and fsync_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y16

 I was hoping I can get a better explaination of this error. When i use the CLOCK_DEDICATED_ROUTE FLASE property I can remove the error but I would like to know that my deisgn will still function.

Does it think that my fsync is a clock? I was using some edge detect statements on that signal which might be confusing the tool. 

Thanks for your help.

-J

[gszakacs]

If the tools have placed a BUFG, it generally means the signal has clock loads.  Note that the gate of an inferred latch is also considered a clock load.  If you don't have any synthesis warnings about latches, then my guess is that the signal is a clock because of the "edge detect statements" in your code.  If you want to post the relevant code, I could possibly comment further.

[lacosteaef]

Here is the body of my RTL. Any additional insight would be great.

Thanks

architecture main of f_grab is
  begin
    process(pclk, fsync)
    begin
    
    if(not falling_edge(fsync)) then
             fsync_out      <= fsync;
             lval_out       <= lval;
             dval_out       <= dval;
             data_out_base  <= data_base;
             data_out_full  <= data_full;
    end if;
    
    if(falling_edge(fsync)) then
        fsync_out <= '1';
        lval_out  <= '1';
        dval_out  <= '1';
    end if;
    pclk_out <= pclk;
    end process;  
end main;

[gszakacs · Accepted solution]

Honestly I'm surprised that this code actually synthesized.  It's not clear what you were trying to describe by (not falling_edge(fsync)) since it means "any time the signal fsync is not transitioning from high to low."  I don't know of any hardware that matches this behavior.  It would be interesting to see what the synthesizer did with this.  In any case I suspect it's not what you wanted.  If fsync is a relatively slow signal (frame sync?) then normally you should use a flip-flop to delay it and detect the falling edge by the signal being high on one clock cycle and low on the next.

[lacosteaef]

The behavior i'm looking for us when fsync (frame sync) goes low i keep it high within the fpga and add in an extra line of information. After the line is added I then bring fsync low.

Thanks,

-J

[lacosteaef]

Perhaps something more akin to this:

    
    if(fsync='0' and reg_fsync='1') then
        fsync_out <= '1';
        lval_out  <= '1';
        dval_out  <= '1';
    else
        fsync_out      <= fsync;
        lval_out       <= lval;
        dval_out       <= dval;
        data_out_base  <= data_base;
        data_out_full  <= data_full;  
    end if;
    pclk_out <= pclk;
    reg_fsync <= fsync;

[lacosteaef]

This now implements without error