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Scholar wzab
Scholar
632 Views
Registered: ‎08-24-2011

Artix7 LVDS output from bank powered from 3.3V

Hi,

I'm fully aware of AR#43989, but I simply need to reuse an Artix7-based board without hardware modification.
I need a differential LVDS-like output from the bank powered from 3.3V.

Of course Vivado does not allow me to select the LVDS25 standard if the power supply voltage is connected to 3.3V, but I can cheat stating that the voltage is connected to 2.5V, while in fact it is connected to 3.3V.

What are the consequences of powering of such bank with LVDS25 outputs from 3.3V? Will it only result in improper common mode voltage (which is negligible with AC coupling)? Will it also increase the differential output voltage?

Or maybe it is dangerous for the FPGA itself? (In fact sometimes it happened to me to set the Vcc for the bank to 2.5V, while in fact it was 3.3V and the FPGA survived it, but maybe it was just by chance...)

TIA & regards,
Wojtek

 

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5 Replies
Xilinx Employee
Xilinx Employee
573 Views
Registered: ‎03-14-2016

Re: Artix7 LVDS output from bank powered from 3.3V

Hello Wojtek,

This operating condition is not supported by Xilinx.  There is no guarentee that this will work or that it won't damage the device.

Looking a simple simulation using the Artix 7, LVDS_25_HR_O driver with Vcc set to 3.3V, I am observing a larger Vdiff swing on the output when compared with Vcc = 2.5V.  As expected the common mode is increased with the higher Vcc voltage.

The simulation indicates that this will be an issue and none of the recommended operating conditions (DS181, v1.25, Table 2) are violated.

You should simulate this setup on your side.

Thank you,
Sam

 

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Scholar wzab
Scholar
554 Views
Registered: ‎08-24-2011

Re: Artix7 LVDS output from bank powered from 3.3V


@samhendr wrote:
The simulation indicates that this will be an issue and none of the recommended operating conditions (DS181, v1.25, Table 2) are violated.

You mean that the operating NONE of operating conditions are violated? Or you wanted to say that NONE of operating conditions are MET? If the first is true, it means that it is possible to work in such mode even though it is not officially supported, and there is no warranty...

Regards,
Wojtek

 

 

Xilinx Employee
Xilinx Employee
542 Views
Registered: ‎03-14-2016

Re: Artix7 LVDS output from bank powered from 3.3V

None of the operating conditions are violated in the simulation.

It is possible to work but it is not officially supported and there is no warranty.

Highlighted
535 Views
Registered: ‎09-17-2018

Re: Artix7 LVDS output from bank powered from 3.3V

Why not use,

A LVCMOS 3.3v 2ma P drive on a pin, and the complement N on an adjacent pin?  Much better solution.  Violates nothing, and quite likely to work with in your design (receiving device most likely to receive it just fine).

l.e.o.

Scholar brimdavis
Scholar
523 Views
Registered: ‎04-26-2012

Re: Artix7 LVDS output from bank powered from 3.3V

@wzab  "If the first is true, it means that it is possible to work in such mode even though it is not officially supported"

Xilinx documentation explicitly states that the 7-series 2.5V differential output buffers automatically tristate for VCCO > 2.85V

UG471 v1.10, Table 1-55, footnote 2, page 100:

2. If the voltage exceeds 2.85V, the outputs will be in a high-Z state. The device should always be operated within the recommended
operating range as specified in the 7 series FPGA data sheets.

> I need a differential LVDS-like output from the bank powered from 3.3V

Offhand, the only 3.3V 7-series differential output buffer I recall is TMDS, available in the HR banks, and requiring external 50 ohm pullups to 3.3V; this might work for some applications if you are AC coupling.

As already mentioned by l.e.o, sometimes you can use two single ended outputs to emulate a differential signal; early FPGA families used an external differential attenuator network to knock down the LVCMOS swing down to LVDS levels, although the common mode would be higher than LVDS specs at 3.3V VCCO when using a differential attenuator, unless you also added some voltage offset using resistors to ground.

-Brian