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Registered: ‎03-16-2014

Artix7 - a rare malfunction of initializing BRAM


I had a strange trouble about initializing BRAM.
The device is Artix7(7a200tfbg676-2). The version
of Vivado is 2015.3 and I set power_opt_design option


I implemented a BRAM as a ROM with an initialization
file. The attached file is a part of the EDIF netlist of the ROM.

This ROM is not initialized correctly once in about
twenty or thirty times. In case of failing, the value
is zero. If power_opt_design is not enabled, this
malfunction doesn't occur.


Basically, this BRAM is implemented as just a ROM,
so its clock input should not be gated... Vivado needs
to exclude this BRAM from gated targets, I think.
This BRAM is gated in the netlist as follows:


  (property IS_CLOCK_GATED (boolean (true)))
  (property POWER_OPTED_CE (string "ENBWREN=NEW"))


But this BRAM is never written(because of ROM),
so its clock input seems to be never triggered
(because ENBWREN is never asserted).

I guess the unusual implementation like this is not
assumed and causes the fail of initialization rarely.


Is this a kind of bug of Artix7 or Vivado? Or I have some



Because I couldn't find the true cause of this problem,
finally I rejected this ROM from the circuit as a workaround.
So the problem has been fixed now, but if possible, I want
to know what causes this rare malfunction for future reference.
In other words, whether BRAM is ALWAYS initialized
correctly even if its clock input is never triggered, or not.


Thank you,

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