09-22-2020 10:06 AM
I am using vivado 2020.1 and FIFO generator 13.2. I implemented "independent clocks built in FIFO" with write data width 1024 and read data with 512. I feed write clock 200MHz and read clock 400Mhz in the design. However, I always got a lot of timing violations on the path from EMPTY to RDEN. Has anyone seen such issue before and any suggestion on it?
09-22-2020 12:16 PM
09-22-2020 01:00 PM
You say the timing violation is from EMPTY to RDEN, not from your read clock to RDEN. Does this mean that the RDEN signal does not come directly from a register? At 400MHz, this may be a problem. How many levels of logic are between a clocked register and the RDEN signal?
09-22-2020 01:43 PM
Oh, I think you are right. The source of the violation path is RDCLK and the destination is RDEN. The violation datapath is shown as:
I actually tied the rd_en of the fifo inst to 1'b1. So I am wondering why there is still a violation. Any idea?