cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
mushihao
Observer
Observer
371 Views
Registered: ‎05-07-2019

Async fifo timing violations using FIFO generator

Hi,

I am using vivado 2020.1 and FIFO generator 13.2. I implemented "independent clocks built in FIFO" with write data width 1024 and read data with 512. I feed write clock 200MHz and read clock 400Mhz in the design. However, I always got a lot of timing violations on the path from EMPTY to RDEN. Has anyone seen such issue before and any suggestion on it?

 

Thanks,

Hao

0 Kudos
4 Replies
drjohnsmith
Teacher
Teacher
355 Views
Registered: ‎07-09-2009

without knowing the device your targeting, or the timing constraints your using, or the error reports, not much we can say,
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
bruce_karaffa
Scholar
Scholar
346 Views
Registered: ‎06-21-2017

You say the timing violation is from EMPTY to RDEN, not from your read clock to RDEN.  Does this mean that the RDEN signal does not come directly from a register?  At 400MHz, this may be a problem.  How many levels of logic are between a clocked register and the RDEN signal?

0 Kudos
mushihao
Observer
Observer
337 Views
Registered: ‎05-07-2019

Oh, I think you are right. The source of the violation path is RDCLK and the destination is RDEN. The violation datapath is shown as:

...gonep.inst_prim/gf36e2_inst.sngfifo36e2/EMPTY

...gonep.inst_prim/gv.gv3.VALID_reg_2[0]

...gonep.inst_prim/empty_INST_0_i_4/O

...gonep.inst_prim/rd_clk_1

...gonep.inst_prim/gf36e2_inst.sngfifo36e2_i_l_rewire_rewire_replica/O

...gonep.inst_prim/RD_EN_repN_alias

...gonep.inst_prim/gf36e2_inst.sngfifo36e2/RDEN

 

I actually tied the rd_en of the fifo inst to 1'b1. So I am wondering why there is still a violation. Any idea?

Thanks,

Hao

 

 

0 Kudos
mushihao
Observer
Observer
336 Views
Registered: ‎05-07-2019

Sorry, I am using VCU128 dev board now. Thanks!

0 Kudos