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embeddedsteve
Observer
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Registered: ‎08-27-2013

Asynchronous or Synchronous Xilinx Macros for synchroniser

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Hi

I am crossing clock domains with a reset signal, i want to replace the current synchronization circuit as it will produce metastability (shown below)

  Synchronisation : process(DCLK_BUFR, reset_i)
  begin
    if rising_edge(DCLK_BUFR) then
      sync_reset <= reset_i;
    end if;
  end process Synchronisation;

 

The new sync_reset signal is used for an asynchronous reset in a process,

 

asynchronus_reset.png

Would i be right in using the Macro "XPM_CDC_ASYNC_RST" to perform correct reset synchronization?

 

Thanks

 

Steve

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kriskoorndyk
Observer
Observer
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Registered: ‎04-24-2019

You can look at the XPM code for the two different reset synchronizers to determine which is appropriate for you.  I'm guessing your reset_i is an asynchronous input to the design, so the answer to your question is likely yes.

<Vivado_Installation>/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv

 

It should be noted that what you've illustrated in the code above is not a traditional reset bridge, but rather a single flop "synchronizer" similar to the xpm_cdc_single, but with only a single flop stage which doesn't really do anything to mitigate a metastability state on either edge of the reset.  You'd be better off with something like this:

Synchronisation : process(DCLK_BUFR, reset_i)
  begin
    if reset_i = '1' then
      reset_sreg <= (others => '1');
    elsif rising_edge(DCLK_BUFR) then
      reset_sreg <= reset_sreg(reset_sreg'left-1 downto 0) & '0';
    end if;
  end process Synchronisation;

sync_reset <= reset_sreg(reset_sreg'left);

 

 

 

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2 Replies
kriskoorndyk
Observer
Observer
558 Views
Registered: ‎04-24-2019

You can look at the XPM code for the two different reset synchronizers to determine which is appropriate for you.  I'm guessing your reset_i is an asynchronous input to the design, so the answer to your question is likely yes.

<Vivado_Installation>/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv

 

It should be noted that what you've illustrated in the code above is not a traditional reset bridge, but rather a single flop "synchronizer" similar to the xpm_cdc_single, but with only a single flop stage which doesn't really do anything to mitigate a metastability state on either edge of the reset.  You'd be better off with something like this:

Synchronisation : process(DCLK_BUFR, reset_i)
  begin
    if reset_i = '1' then
      reset_sreg <= (others => '1');
    elsif rising_edge(DCLK_BUFR) then
      reset_sreg <= reset_sreg(reset_sreg'left-1 downto 0) & '0';
    end if;
  end process Synchronisation;

sync_reset <= reset_sreg(reset_sreg'left);

 

 

 

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embeddedsteve
Observer
Observer
547 Views
Registered: ‎08-27-2013

Thanks for your response, yes reset_i is asynchronous so i will go ahead with the Macro.

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