Available I/O standard in bank using DCI cascade

[blingbling-eyes]

Hello,

I am designing a board using XC7K325T. I will cascade the DCI of the three HP banks, and I intend to use the two memory controllers to connect the DDR3. Here, I want to put the sys_clk needed for MIG into LVDS to DCI master bank. The Vcco voltage of the bank is 1.5V. I would like to know if there are any restrictions to allow LVDS signals to be input from a DCI cascaded bank for DDR3. 

Thanks.

[klumsde]

You can put an LVDS input in this bank because there is no requirement on VCCO. 

The only thing is you can't use the on chip DIFF_TERM you will need to terminate it on the board. 

Please see this AR

https://www.xilinx.com/support/answers/43989.html

Keith 

[blingbling-eyes]

Thank you for your quick response.

Do you mean that I can connect like this?

Also, UG586 page 211 states that it is also possible to connect such as figure below.

 however, UG586 page 211 says that it is also possible to link to the figure below.

Is it both possible?

Additional questions.

What are the I/O standards that can be used in a bank using DCI (VCCO=1.5V) ? 

Is it possible to use all I/O standards that drive at 1.5V voltage without termination?

Thanks.

[klumsde · Accepted solution]

You can do like what is in figure 1-70

However, if your signal input common mode and singled ended swing add up such that you will violated the VIN recommendation then you need to AC couple like the figure 1-95. 

if you have a 1.5V bank you could make use of LVCMOS15 inputs or outputs. 

The best thing to do is put this proposed pinout into a vivado pin planning project and then run a DRC to check it is valid. 

[blingbling-eyes]

Thanks Klumsde.