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lokesh_oepl
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Registered: ‎03-12-2018

AxiCDMA Scatter Gather Mode is not working

Hi there,

I was working with Axi CDMA simple transfer since while. In the beginning, I was struggling with the data transfer through CDMA but as mentioned in the following link now I'm able to do the data transfer. 

here's the link : https://forums.xilinx.com/t5/AXI-Infrastructure/CDMA-is-not-transfering-data-from-BRAM-to-DDR/m-p/874333#M1349

With the help of following Block Diagram and Address Map, I'm able to transfer data through CDMA from DDR to BRAM and vise-versa using Simple Transfer Poll Mode (without Scatter Gather).

Capture1.JPGCapture3.JPG

Now, I wanted to use the same design and transfer the data through CDMA but in Scatter-Gather Mode. for that I've tried the template code provided by xilinx. With the help of that code I'm able to transfer the data from one location of DDR to another location of DDR in Scatter Gather mode. So I don't see any problem in the template code. But the ultimate goal is to transfer the data between DDR and BRAM.

So, in the same code, I've kept DDR  as destination address and BRAM as source address. But this scenario is not working as DDR to DDR works fine.

In short,

What is working with above Block Design??

  1. Simple Transfer from DDR to Bram and BRAM to DDR without Scatter Gather
  2. Data Transfer from DDR to DDR with Scatter Gather

 What is not working??

  1. Data Transfer from BRAM to DDR or DDR to BRAM with Scatter Gather

 Looking forward to any positive response..

Thanks and Regards,

Lokesh_OEPL

 

Lokesh J.
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lokesh_oepl
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Registered: ‎03-12-2018

Hellow there,

I'm extremely sorry Folks, actually I've uploaded the wrong project's Snapshots. 
Please find the attachment for the correct snaps.

Screenshot from 2018-11-23 10-25-59.jpgScreenshot from 2018-11-23 10-26-09.jpg

 

 

 

Thnaks

Lokes_OEPL

Lokesh J.
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lokesh_oepl
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Registered: ‎03-12-2018

Hi there,

Please find the attachment for the template code I was talking about which is provided by the xilinx on the following path in my laptop.

C:\Xilinx\SDK\2017.4\data\embeddedsw\XilinxProcessorIPLib\drivers\axicdma_v4_3\examples\xaxicdma_example_sg_poll.c

In that code I've changed the following things to made it working for BRAM to DDR data transfer.

#define MEMORY_BASE		0x01000000

#define TX_BUFFER_BASE		0xC0000000 //(MEMORY_BASE + 0x00630000)
#define TX_BUFFER_BASE_PS	0x40000000
#define RX_BUFFER_BASE (MEMORY_BASE + 0x00660000)

0x40000000 address of BRAM is visible to PS, so I'm writing some known data to it.

Similarly 0xC0000000 address of BRAM is visible to CDMA, this address is used for transmitting the BRAM data to DDR. 

Can anyone help me to resove this, as the DDR to DDR is working and BRAM to DDR is not.

 

Thanks

Lokesh_OEPL 

 

 

Lokesh J.
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