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Visitor xieb211
Visitor
345 Views
Registered: ‎06-02-2019

BUFGMUX output stays on high?

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I meet a issue of BUFGMUX.

I use a device of XC7K70T-2FBG484C, and VIVADO version is 2018.2.

I want to output a clock selected from four clocks. The design is below. Clk1, clk2 and clk3 are output of a same MMCM, MMCM1. Clk4 is output of another MMCM, MMCM2.

BUFGMUX #(
)
BUFGMUX_inst0 (
.O (clk_out0 ),
.I0 (clk1 ), 
.I1 (clk2 ), 
.S (clk_sel0 )
);

BUFGMUX #(
)
BUFGMUX_inst1 (
.O (clk_out1 ), 
.I0 (clk3 ), 
.I1 (clk4 ), 
.S (clk_sel1 ) 
);

BUFGMUX #(
)
BUFGMUX_inst2 (
.O (clk_out2 ),
.I0 (clk_out0 ), 
.I1 (clk_out1 ),
.S (clk_sel2 )
);

When MMCM has on input, clk1, clk2 and clk3 has no clock signals on them. But clk4 has a clock of 50M.

I make certain clk_sel0=1, clk_sel1=1, clk_sel2=1, and I want to select clk4 as the output. But the clk_out2 is high(1), it isn't a clock of 50M. 

I output the 3 clk_sel, 3 clk_out to the test points and measure using a oscilloscope. 3 clk_sel are the right value.

But clk_out0 is high(1), clk_out1 is high(1), and clk_out2 is also high(1).

But when I give a input clock to MMCM1, clk_out2 comes the clock of 50M.

 

Is this a BUG?

 

Thanks.

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1 Solution

Accepted Solutions
Moderator
Moderator
311 Views
Registered: ‎08-08-2017

Re: BUFGMUX output stays on high?

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Hi @xieb211 

Both clocks should be active for BUFGMUX to show the expected output.

The BUFGMUX timing diagram and switching process from UG is

https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf

 

Capture.JPG

to confirm this i will try to replicate your problem here.

When MMCM has on input, clk1, clk2 and clk3 has no clock signals on them

Can you elaborate on this ?  are the clk1, clk2 and clk3 are constant "HIGH" or constant "LOW?

 

 

 

 

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------
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5 Replies
Moderator
Moderator
312 Views
Registered: ‎08-08-2017

Re: BUFGMUX output stays on high?

Jump to solution

Hi @xieb211 

Both clocks should be active for BUFGMUX to show the expected output.

The BUFGMUX timing diagram and switching process from UG is

https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf

 

Capture.JPG

to confirm this i will try to replicate your problem here.

When MMCM has on input, clk1, clk2 and clk3 has no clock signals on them

Can you elaborate on this ?  are the clk1, clk2 and clk3 are constant "HIGH" or constant "LOW?

 

 

 

 

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------
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Scholar drjohnsmith
Scholar
300 Views
Registered: ‎07-09-2009

Re: BUFGMUX output stays on high?

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Can I ask why you want to do this ?

the delay to the selected clock is going to be big,
and as your just driving it out, the mark space ratio will not be that good.

If you only want to monitor the clock,
try dividing the clocks by say 4, and then select between the divided outputs to output, using a normal case statement / mux.



<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Visitor xieb211
Visitor
288 Views
Registered: ‎06-02-2019

Re: BUFGMUX output stays on high?

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Hi,  ,

Thanks for your reply.

I have read the datasheet about the picture you attached. But I think this is a  switching process. That is, if I want to switch the clock output, the below steps should be accomplished.

But I set the clk_sel1=1 as a power up reset value. There will not be such a switching process. Dose the power up reset output is I0? If so, then the output also should go through a switching process.

So, I will try again as below:

move the clk4 to the I0 of BYFGMUX1, and move the clk_out1 to I0 of BUFGMUX2. clk1, clk2, clk3 are still maintain no clocks.

I will feedback the test result.

 

I' m sorry I make a little mistake, When MMCM has on input, the MMCM should be MMCM1, who generate clk1, clk2 and clk3.

When no input to MMCM1, I don't know exactly whether clk1, clk2 and clk3 are all "HIGH" or “LOW”. I didn't output them to test pins to measure.

But I output the clk_out0 and clk_out1 to test pins to measure. They are "HIGH". So I think, clk1, clk2 and clk3 should also be "HIGH".

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Visitor xieb211
Visitor
283 Views
Registered: ‎06-02-2019

Re: BUFGMUX output stays on high?

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Hi drjohnsmith,

I receive a input Vedio data from a Scaler IC by 4 LVDS channels. There is 5 lanes in each LVDS channel. 

The Scaler IC transmits the vedio data may use only 1 LVDS channel, or 2 LVDS channels, or 4 LVDS channels, in different vedio resolution.

The output is TTL vedio interface. I should combine input data from all channels. So the output data clock will be x1, or x2, or x4 times of input clock. Clk1, clk2, clk3 is the x1, x2, x4 times clock accordingly, they are generated by the same MMCM.

Clk4 is generated by another MMCM, whose input is 200M system clock.

So, when there is no input vedio data, that is no input clock, I want to output clk4.

Thanks.

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Visitor xieb211
Visitor
274 Views
Registered: ‎06-02-2019

Re: BUFGMUX output stays on high?

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Hi,  

I have finished the test. The result is OK.

I changed the clk4 connecting to I0 of BUFGMUX1, and clk_out1(the output of BUFGMUX1)  is connected to I0 of BUFGMUX2.

Still remain the clk1,clk2, clk3 have no clocks on them(that is, they are all HIGH). 

This time, I get the final output (clk_out2) of clk4.

 

UG472 does not say that the default output of BUFGMUX is I0. But this is the fact.

So, even the power up value of S is '1', there still need a switching process to output I1.

 

Thank you very much.

 

 

 

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