BUFGT followed by BUFG

[crochetx]

Hi,

I'm using the ZC706 with a board on the FMC. I need a clock from that board, but it comes from a pin connected to a GT buffer.

So, after reading the Gigabit Transceiver doc, I realized I could clock the PL thanks to a BUFGT, if it is followed by a BUFG.

I did that but it doesn't work. I keep trying but I get nothing.

Can you confirm that what I'm trying to do is possible? If so, what did I do wrong?

Thanks.

[roym]

BUFG's should all have the same reach.  I don't find BUFGT in the catalog.  BUFG_GT would be ultraScale.  I suspect it has something to do with the pin you are trying to reach.  Which one is it?

[crochetx]

By BUFGT, I mean IBUFDS_GTE2.

I simply connect the output of the IBUFDS_GTE2 to a BUFG. Here is my code:

    IBUFDS_GTE2_inst2 : IBUFDS_GTE2
        generic map (
            CLKCM_CFG => TRUE,
            CLKRCV_TRST => TRUE,
            CLKSWING_CFG => "11"
        )
        port map (
            O => refclk,
            -- ODIV2 =>
            CEB => '0',
            I => refclk_p,
            IB => refclk_n
        );
         
    refclk_bufg_inst : BUFG
        port map (
          O => core_clk, -- 1-bit output: Clock output
          I => refclk  -- 1-bit input: Clock input
       );

Then I try to use the core_clk, but I see no clock.

[borisq]

hi @crochetx 

you can try instantiate a GT (COMMON and CHANNEL) and see if the GT PLLs can lock.

Thanks,

Boris

[crochetx · Accepted solution]

I've just retried it with another IBUFG_GTE2 and it works.

In fact, the pins I was using are not connected to the FPGA because of a mounting option.

Sorry, my mistake.

Anyway, thanks for your help.