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Newbie puurjitdasa
Newbie
3,605 Views
Registered: ‎01-19-2018

Basys3 - Creating a 10 seconds period clock

Hello,

 

I am new to FPGA and bought a basys 3 board to learn. I want to create a clock that has a 10 seconds period. The reason I want such a low frequency is because I am making a d flip flop and want to be able to see if my code works.

 

I tried using the basys 3 xdc constraint files and editing it:

 

set_property PACKAGE_PIN W5 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
create_clock -add -name sys_clk_pin -period 5e+9 -waveform {0 2.5e+9} [get_ports clk]

 

However when I try generating the bitstream, it throws an error. The log has many errors, the first of which is:

WARNING: [Vivado 12-584] No ports matched 'clk'

 

On the other hand, when I replace mentions of sys_clk_pin in my VHDL design source code with 'clk', it works but I suspect it is running at the default clk frequency.

 

How do I solve this error?

Thank you.

0 Kudos
2 Replies
Mentor jmcclusk
Mentor
3,594 Views
Registered: ‎02-24-2014

Re: Basys3 - Creating a 10 seconds period clock

What you are asking is actually somewhat difficult, because a 10 second clock is far slower than is normally used.  It can be done, however.  There is already a 100 MHz oscillator on pin W5.  i.e. 

 

The Basys3 board includes a single 100MHz oscillator connected to pin W5 (W5 is a MRCC input on bank 34). The input clock can drive MMCMs or PLLs to generate clocks of various frequencies and with known phase relationships that may be needed throughout a design.

 

Take this 100 MHz clock, and divide it by 10^9, and you'll have a 10 second clock.  It's easy enough to divide it down..  first divide by 500 milliion, and use the overflow pulse to toggle the 10 second clock,  which will be nice and symmetric.

 

VHDL:

 

use ieee.numeric_std.all;

...

constant C_reload_value : unsigned(31 downto 0) := to_unsigned( 500000000 - 2, 32);

signal  counter : unsigned(31 downto 0) := C_reload_value;

signal  clk_10s : std_logic := '0';

begin

process(clk)

begin

  if rising_edge(clk) then

     if counter(31)='1' then

        counter <= C_reload_value;

        clk_10s <= not clk_10s;

     else

        counter <= counter - 1;

     end if;

 end if;

end process;

 

 

Don't forget to close a thread when possible by accepting a post as a solution.
Moderator
Moderator
3,569 Views
Registered: ‎09-18-2014

Re: Basys3 - Creating a 10 seconds period clock

puurjitdasa,

 

Create_clock is just a clock constraint used for timing analysis. It doesn't actually create a clock out of thin air. You need to actually create some logic to do this. It's sort of a little hack but completely doable. I see that you are trying to already generate a bitstream! Have you tried simulating it first to make sure your logic looks to be doing what you expect? Clock speeds are far too fast these days to actually see the toggling with the naked eye. In order to do what I think you want to do, I agree with Jmcclusk. You will essentially need to create some counter logic to track each clock cycle of your board input clock but only register or act on it every nth cycle or edge. You will need to calculate how many of your input clock cycles is 10seconds and use that in your counter a base to when to register a toggle.  Essentially you are slowing down the actual rate of logic operation wasting a lot of clock cycles but that is what is needed to be done to slow down a fast toggle signal to be seen with the naked eye. In any case, I suggest simulating it before even trying to generate the bitstream to make sure your logic is sound so that you are not disappointed when you load an image that does not work the way you intended it to. There are loads of references on the web that show you how to leverage counters to divide clocks down and other cool implementations. 

 

http://www.fpga4fun.com/Counters.html

 

http://www.fpga4student.com/2017/03/verilog-code-for-counter-with-testbench.html

 

 

Regards,

T

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