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Adventurer
Adventurer
348 Views
Registered: ‎10-12-2018

Best Output Clock Generation Method

Hi to all,

I am designing for Kintex 7 and I need to generate a perfect output 100MHz clock. Currently, I am generating it using ODDR2 but it has some jitter.

What is the best way to do that?

Thank you very much in advance.

 

Kindest Regards,

Amir

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Registered: ‎01-22-2015

@amir.massah 

You’ll find lots of discussion and some test results about jitter of clocks created by a 7-Series FPGA in the following thread.

https://forums.xilinx.com/t5/Other-FPGA-Architectures/FPGA-creates-main-clock-for-ADC/td-p/857807

Mark

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Teacher
Teacher
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Registered: ‎07-09-2009

what do you mean by perfect ?

ODDR2 is the way to do it,

the limiting factor is going to be what are you driving the clock to the ODDR2 with,

Be certain to use a PLL, and use the low jitter output option,

What is the jitter your getting ?

Can you post screen shot from the scope or spectrum analyser your using to measure this,

Ultimately, FPGAs are not the best way of generating a clock for something like and ADC.

If its is an ADC your driving, whats the number of bits and analog bandwidth of the ADC,



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Teacher
Teacher
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Registered: ‎06-16-2013

Hi @amir.massah 

 

What criteria does "a perfect output 100MHz clock" mean ?

Perfect duty ? Less clock jitter ? Need to concern variation ?

 

If my understand is correct, I suggest you to make sure a clock source of ODDR2.

 

Best regards,

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Adventurer
Adventurer
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Registered: ‎10-12-2018

Hi to all,

I mean low jitter and 50-50 duty cycle by perfect. 

For my clock source, I am using PLL and the with enabled optimum output jitter option.

Kindest Regards,

Amir

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