Bit-level deskewing of the clock line instead of the data lines
Hi All, We have a design with DDR LVDS receiver, 288 MHz, data is stable around the clock edge, with setup and hold time being EACH 420 ps.
We are using one of our previous designs for clock calibration and bit-level deskewing, i.e. 1. We first find the clock edge by tap adjustment similarly to XAPP585 and XAPP1017 but with different serialization ratio, and then apply the tap setting to the data line's IDELAYE2 2. Then later on, we kick in the bit-level deskewing of the data lines
The design works so far and it is based off the KC705 with a little bridging board, with I would think worse signal integrity then final product, which will use the Artix-7 A35 with -2 speed grade, and if it means anything, DIFF_HSTL 1.8V.
Currently, the design seems to work just fine with just the clock calibration (i.e. step 1 only) and without the per-line bit-level deskewing.
I thought of a possibility of applying the bit-level deskewing to the clock instead of the data - would it make sense in this case of data centered around the clock edge to implement a bit-level deskewing of the clock line alone and apply the deskewed tap values to the data?