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usman1818
Observer
Observer
4,983 Views
Registered: ‎10-12-2016

Block RAM (failed timing)

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Hi All,

 

I am using nexys-4(Artix-7) board. With IP integrator, i configure the BRAM as a simple dual port ram, so its component declaration cereated by IP integrator is;

------------------------------------------

COMPONENT blk_mem_gen_1
  PORT (
    clka : IN STD_LOGIC;
    wea : IN STD_LOGIC;
    addra : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
    dina : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
    clkb : IN STD_LOGIC;
    addrb : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
    doutb : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
  );
END COMPONENT;

--------------------------------------------------------

This is running perfectly with my design but i have a problem with timing. Timing report states that there is a negative slack in my block ram source and destination(see attached file). Funny thing is that these source and destination doesn't exist in my block ram because i didn't configure them. Source is CLKARDCLK which is read clk of A port but I can only write to A port (because of SDP, I cann't read from A port). Destination is DIBDI which is data in of B port but I cann't write to B port. Any idea what's going on here?? Note: this block is running perfectly with my design... 

Regards

Usman 

 

timing.jpg
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1 Solution

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keisn13
Observer
Observer
8,481 Views
Registered: ‎10-28-2013

your expression : 

 

avg_ram_data_s   <= ((ram_wr_data_i & X"0000") * new_pwm_factor) + (avg_ram_data_o_s(47 downto 16) * avg_pwm_factor);

 

creates many logic levels. Try separate this expression and include some DFF between separated stages. Or try use dsp resources of your fpga.

 

--

sorry for my english

--

View solution in original post

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6 Replies
htsvn
Xilinx Employee
Xilinx Employee
4,964 Views
Registered: ‎08-02-2007

hi,

 

would that be possible to share the design? 

 

--hs

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usman1818
Observer
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4,942 Views
Registered: ‎10-12-2016

Hi,

Thanks for your reply. Sorry I cannot share the whole design. But I can explain it more to you. Tool is vivado 2016.3, frequency is 100 MHz. I attached all timing errors' pic. Data is coming from uBlaze(ethernet interface), I do some calculations and store it to SDP ram. Then after reading from SDP, I send this data to uBlaze again. Its simple.

 

Regards

Usman

timing.jpg
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keisn13
Observer
Observer
4,905 Views
Registered: ‎10-28-2013

Maybe problem in that you have 19 levels of logic?

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usman1818
Observer
Observer
4,898 Views
Registered: ‎10-12-2016

I don't know about logic level but the following statement is complete logic.

 

avg_ram_data_s   <= ((ram_wr_data_i & X"0000") * new_pwm_factor) + (avg_ram_data_o_s(47 downto 16) * avg_pwm_factor);

 

where

avg_ram_data_s 48 bits wide,

ram_wr_data_i 16 bits

pwm_factors are 16 bits

avg_ram_data_o_s 48 bits.

 

I just see the synthesized design's schematic(attached) and I am surprised that those both signals are connected. I need to debug it deeply.

 

ram.jpg
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keisn13
Observer
Observer
8,482 Views
Registered: ‎10-28-2013

your expression : 

 

avg_ram_data_s   <= ((ram_wr_data_i & X"0000") * new_pwm_factor) + (avg_ram_data_o_s(47 downto 16) * avg_pwm_factor);

 

creates many logic levels. Try separate this expression and include some DFF between separated stages. Or try use dsp resources of your fpga.

 

--

sorry for my english

--

View solution in original post

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usman1818
Observer
Observer
4,870 Views
Registered: ‎10-12-2016

Hi keisn13,

 

Thanks for the suggestion. I use DSP resources for this calculation and timing errors has gone away. Thanks again.

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