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Visitor
Visitor
3,027 Views
Registered: ‎07-22-2017

Bram in scan chain

Hi,

 

I have a design in which I need to insert a scan chain between a bram and some registers. For example I would following structure: 

 

jtag-tap ---> bram --->reg0--->reg1--->. . .--->regN--->jtag-tap.

 

I have three questions:

1) Is there the scan-in and scan-out pin on bram ip, or should i use a bram controller and interfacing with axi? 

2) Is Jtag To Axi Master a jtag tap for axi interface?

3) If this solution can not be implemented, how can I do this with Vivado Ip Integrator?

 

Thank you.

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Guide
Guide
2,969 Views
Registered: ‎01-23-2009

So, it is really unclear what you are trying to accomplish.

 

The concept of a "scan chain" doesn't really exist within the FPGA. Yes, there are serialized management structures for loading the bitstream and doing some other options, but they aren't (at least directly) user accessible. So I don't understand what you mean by "I need to insert a scan chain..." - for what reason.

 

The BRAM definitely does not have a SCAN_IN/SCAN_OUT - again, because there are no scan chains in the FPGA; scan chains are an ASIC testing feature...

 

As for the rest of your questions regarding AXI masters and IP integrator, you need to describe what you need done? Are you trying to access the values of the BRAM from a PC in real time?

 

Avrum

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Visitor
Visitor
2,941 Views
Registered: ‎07-22-2017

Then I'll explain it better:

my intent is to create a structure for debugging a core after implementation. So I need to create a "scan chain" between some core registers and bram, JTAG compliant, in order to inject values in the core pipe, out of the normal running stream of the core. Now to simplify this work I ask you the better way to implement this with ip core. Is it possible?  

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Guide
Guide
2,894 Views
Registered: ‎01-23-2009

For the most part, you haven't really given much more information. You are still telling us how you want to do something, not what you want to do.

 

If you want to "debug" a core, there are already mechanisms in the FPGA that help with debugging; the Vivado ILA and VIO cores are a few. There are also cores that can be inserted into an AXI system to inject operations into the network.

 

But none of these are "scan chains" and are not "JTAG compliant" in the traditional sense. They use the JTAG connection between Vivado and the target board, but use custom JTAG registers with a Xilinx proprietary format to interface with the cores.

 

Even with these, you cannot "inject values ... out of the normal running stream of the core". Specifically the BRAM has two and only two ports (the A and B ports, assuming the RAM is dual ported) - there is no other mechanism to access the internals of the RAM, and there is no "scan" mechanism.

 

Avrum

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Visitor
Visitor
2,873 Views
Registered: ‎07-22-2017

Thank you very much! You've solved my problems.

 

Gjei

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