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rickwen77
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Visitor
3,063 Views
Registered: ‎09-02-2016

CAN'T set IOSTAND to LVDS_25 in HR bank (Vcco=2.5V)

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Hi,

 

In my design, the input signals are connected to the KC705 evaluation board as LVDS. I tried to set the IOSTANDARD as LVDS_25 since they are connected to HR bank. But unfortunately, the I/O type in the implemented design can't be set to LVDS_25 which results in BITGEN failure. Below is the constrains:

 

set_property DIFF_TERM TRUE [get_ports XX_clk_n]
set_property PACKAGE_PIN C27 [get_ports XX_clk_n]
set_property IOSTANDARD LVDS_25 [get_ports XX_clk_n]
set_property DIFF_TERM TRUE [get_ports XX_clk_p]
set_property PACKAGE_PIN D27 [get_ports XX_clk_p]
set_property IOSTANDARD LVDS_25 [get_ports XX_clk_p]

test.bmp
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pratham
Scholar
Scholar
5,301 Views
Registered: ‎06-05-2013

@rickwen77 The reason you are not able to apply those constraint is because these ports are not differential to each other as per your RTL.

 

You have to instantiate the IBUFDS.

 

Example: 

 

IBUFDS_inst : IBUFDS
generic map (
DIFF_TERM => FALSE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => refclk, -- Buffer output
I => clkp, -- Diff_p buffer input (connect directly to top-level port)
IB => clkn -- Diff_n buffer input (connect directly to top-level port)
);

 

You can also refer discussion here

 

https://forums.xilinx.com/t5/Implementation/How-do-I-tell-Vivado-that-my-signal-is-differential/td-p/332731

 

After this you can open the implemented design and apply the iostandard. 

 

-Pratham

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vemulad
Xilinx Employee
Xilinx Employee
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Registered: ‎09-20-2012

Hi @rickwen77

 

Are these differential ports? Do you have IBUFDS/IBUFGDS instantiated in RTL? 

 

From the snapshot it looks like the tool is not recognizing these ports as differential hence it is not allowing to select differential IO standard LVDS_25

Thanks,
Deepika.
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pratham
Scholar
Scholar
5,302 Views
Registered: ‎06-05-2013

@rickwen77 The reason you are not able to apply those constraint is because these ports are not differential to each other as per your RTL.

 

You have to instantiate the IBUFDS.

 

Example: 

 

IBUFDS_inst : IBUFDS
generic map (
DIFF_TERM => FALSE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => refclk, -- Buffer output
I => clkp, -- Diff_p buffer input (connect directly to top-level port)
IB => clkn -- Diff_n buffer input (connect directly to top-level port)
);

 

You can also refer discussion here

 

https://forums.xilinx.com/t5/Implementation/How-do-I-tell-Vivado-that-my-signal-is-differential/td-p/332731

 

After this you can open the implemented design and apply the iostandard. 

 

-Pratham

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

View solution in original post

forum.JPG
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