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Observer
Observer
1,638 Views
Registered: ‎11-14-2008

CLKOUT4_CASCADE still not supported by the Clocking Wizard IP in Vivado 2017.4 ?

Hello,

 

 

it looks like the Clocking Wizard IP is still not supporting the use of the CLKOUT4_CASCADE feature ?

 

When I enter a relative low output frequency for clk_out4 (e.g. 2.5 MHz), that would require the use of the CLKOUT4_CASCADE feature, the wizard just tells me that it is out of range; it seems not intelligent enough to use the div4/div6 cascade feature.

Perhaps I should configure something for the clk_out6 output??

There is also a tab to override MMCM settings (and where the cascading could be enabled), but this seems not to fix the warnings...

 

A search on the internet and on this forum reveals that this issue is already reported by users many years ago.

 

 

Target device is a Zynq7020

 

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Scholar
Scholar
1,628 Views
Registered: ‎02-27-2008

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Observer
Observer
1,624 Views
Registered: ‎11-14-2008

Hi Austin,

 

yes of course I came across that thread...

and yes of course I could directly instantiate the MMCM with all relevant features, but it would be more logical if it would be supported in the wizard...

 

I just want someone from Xilinx confirm that the wizard in 2017.4 is still not supporting the CLKOUT4_CASCADE feature; or that it does support it but that you have to use it in a particular way...

 

Best regards,

Jon

 

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Scholar
Scholar
1,614 Views
Registered: ‎02-27-2008

OK,

 

Just checking.  The data sheet does indicate 2.5 MHz should be possible (in range).  I will ping the moderator for this topic.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Scholar
Scholar
1,603 Views
Registered: ‎02-27-2008

What is your input clock frequency?

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Xilinx Employee
Xilinx Employee
1,591 Views
Registered: ‎10-11-2007

In Vivado2017.4 at least it's supported for UltrascalePlus for sure. Go to the MMCM Settings tap, click "Allow Override Mode" and then checkbox the last entry in the table "CLKOUT_CASCADE". I don't remember exactly when that was added.

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Moderator
Moderator
1,578 Views
Registered: ‎09-18-2014

jods,

 

This issue was not fully transparent to Xilinx otherwise it would have been fixed long ago. This particular issue looks to have slipped through the cracks in that the fix was somehow only applied to the newer Utrascale devices. I will file a Change Request to get this working in a future version of the wizard most likely 2018.X. For now, the workaround would be to use MMCM in manual mode to get CLKOUT4_CASCADE working. Another option is to use the CoreGen clocking wizard in ISE assuming you are using a 7-series or older device. 

 

 

Regards,

Tezz

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Observer
Observer
921 Views
Registered: ‎01-26-2009


@tenzinc wrote:

jods,

 

For now, the workaround would be to use MMCM in manual mode to get CLKOUT4_CASCADE working. 

 

 

Regards,

Tezz



Hi. I am in a similar position, having need for the clock cascade feature to program a Virtex 7 part. It's just one little line of code! Why isn't it supported in the wizard?

 

Is there some way to copy the output files of the clocking wizard and incorporate its source code into my design without me having to entirely re-code the MMCM and AXI interface myself? I hate reinventing wheels.

 

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