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Visitor schroeca
Registered: ‎06-27-2012

CSI2 interfacing



i want to connect a CSI2 D-PHY compliant imager directly to the FPGA. In the I/O specification it is stated, that the differential voltage on the input (Vid: Q-nQ) should not be higher than 600 mV. 

In the CSI2 specification it is mentioned that a receiver must be capable of handling a voltage of 1.3V max. This is necessary to detect a start condition for an high speed transmission. 

To handle this case the standard recommends to en/disable the differential termination. But this is not possible with the FPGA.


Is there any recommendation on how to connect to an CSI2 D-PHY compliant IC?

Is it allowed to have a differential voltage of 1.3V for a short period of time? In my case this would mean a current of 13mA flowing across the internal diff_term.

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Teacher muzaffer
Registered: ‎03-31-2012

Re: CSI2 interfacing

Check out this document; http://www.edn.com/design/communications-networking/4368073/Implementing-an-SLVS-transceiver

it might help.
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