UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor schroeca
Visitor
2,880 Views
Registered: ‎06-27-2012

CSI2 interfacing

Hi,

 

i want to connect a CSI2 D-PHY compliant imager directly to the FPGA. In the I/O specification it is stated, that the differential voltage on the input (Vid: Q-nQ) should not be higher than 600 mV. 

In the CSI2 specification it is mentioned that a receiver must be capable of handling a voltage of 1.3V max. This is necessary to detect a start condition for an high speed transmission. 

To handle this case the standard recommends to en/disable the differential termination. But this is not possible with the FPGA.

 

Is there any recommendation on how to connect to an CSI2 D-PHY compliant IC?

Is it allowed to have a differential voltage of 1.3V for a short period of time? In my case this would mean a current of 13mA flowing across the internal diff_term.

Tags (3)
0 Kudos
1 Reply
Teacher muzaffer
Teacher
2,867 Views
Registered: ‎03-31-2012

Re: CSI2 interfacing

Check out this document; http://www.edn.com/design/communications-networking/4368073/Implementing-an-SLVS-transceiver

it might help.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
0 Kudos